Theory and Methodology for Performance-Driven Automation in RTL and Testbench Debugging

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The semiconductor industry has products reaching all aspects of commercial and consumer markets domestically and internationally. It consistently creates smaller, faster and more powerful integrated computer Very Large Scale of Integration (VLSI) chips which fuel the accelerated demand of the end products. Chip companies are challenged to design increasingly complex devices while remaining cost competitive. Computer-Aided Design (CAD) tools are continuously improving their efficiency to mitigate this cost. In the past decade, the effort to verify the correctness of these systems has increased disproportionately and takes as much as 70% of the total design cycle, a trend coined the verification gap. This is also confirmed by the 3:1 ratio between the number of verification engineers versus that of designers in the semiconductor industry, a trend that has been projected to increase almost two-fold by 2015. When verification fails and the design is proven to be incorrect, debugging follows to identify the source of the error and fix it. Today, this is a predominantly manual task. As technical roadmaps and research studies indicate, the resource-intensive manual debugging has become the most significant component of the verification gap taking as much as 32% of the total verification time. That is, for a typical design cycle of 18 months, engineers today spend 4-5 months in manual debugging. Evidently, this introduces disproportional non-recurring costs and it may jeopardize the chip delivery day. Consequently, it comes as no surprise that debugging was recently pronounced the central theme in verification R&D for the next 5-6 years by the CEO of Synopsys, the largest Electronic Design Automation CAD tool vendor. Our group was the first to recognize this emerging trend ten years ago. In 2005 we proposed the first automated debugging theory and methodology that today is used and referenced by peer research groups and industry worldwide. In this proposal we leverage this investment to investigate new theories for formal CAD tools and respective methodologies for the modern chip verification/debug cycle. These tools will utilize robust engines and proprietary data mining algorithms to exhaustively analyze the big data generated by verification to ensure correctness of the design. The end result will be the theory and a CAD tool that can be deployed in any industrial semiconductor site to aid the engineers during debugging. This ambitious and multi-disciplinary project promises major theoretical advances and practical applications that instill benefit in CAD for VLSI but also in other fields of science such as software verification, data mining and artificial intelligence. Further, due to the continuous growth of semiconductor industry, there has been a shortage of Highly Qualified Personnel (HQP) in digital VLSI verification/debug that remains strong at all levels of education (PhD, MASc, BASc). Hence, it comes as no surprise that there continues to be much industrial, political and educational attention within Canada devoted in training of HQP in related areas. Everybody involved with the development of the technology will gain knowledge in advanced CAD concepts, practical VLSI verification, hands-on experience and strategic planning. Our pioneering R&D environment and collaboration with the industry will offer them an unparalleled experience in innovation. Graduate students will publish in prominent scientific conferences/journals with strict acceptance criteria and they will gain international visibility. As shown by the post-graduation employment success of our alumnus, this HQP will gain knowledge at the forefront of technology and they will exercise it in a way beneficial to the Canadian society and economy.