Accelerating Data Analytics Through Emerging Software-Hardware Mechanisms

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The objectives of this research are to investigate algorithms, design, and architectures for enabling an efficient real-time event data analytics platform to support multi-query processing over high-volume and high-frequency event streams. To achieve these objectives, we plan to leverage modern hardware mechanisms, such as Field Programmable Gate Arrays (FPGAs) and Application Processing Units (APUs) in our design. We strive to achieve line-rate multi-query processing by exploiting unprecedented degrees of parallelism and potential for pipelining, only available through custom-built, application-specific and low-level logic design. Furthermore, we intend to compare against the use of emerging Graphical Processing Units (GPUs) in our design, evaluating above all performance, but also development effort. The need for efficient real-time analytics is an integral part of a growing number of data management problem scenarios such as business analytics, big data processing, and complex event processing. Common among all these scenarios is a predefined set of continuous queries and an unbounded event stream of incoming data that must be processed against the queries in real-time. However, the vision of enhancing data analytics computations with FPGAs has a few caveats that make acceleration a challenging undertaking. First, current FPGAs are still much slower compared to commodity CPUs. Second, the accelerated application functionality has to be amenable to parallel processing. Third, the on-/off-chip data rates must keep up with chip processing speeds to realize a processing speedup by keeping the custom-built processing pipeline busy. Finally, FPGAs restrict the designer's flexibility and the application's dynamism, both of which are hardly a concern in standard software solutions. By meeting these challenges in our approach, we propose an FPGA-based real-time analytics platform that supports line-rate processing of data streams over a collection of continuous queries. We plan to explore this problem space along the following three dimensions: (1) Design high-throughput, custom circuits to implement the relational algebra operators, (2) design multi-query optimization techniques amenable to the features offered by FPGAs, (3) design software-to-hardware multi-query processing techniques that map a set of queries into a global query plan for processing by our custom circuits.