Error Resilient Machine Learning Systems

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Self Driving Cars (SDCs) or autonomous vehicles have become increasingly popular, and they promise to revolutionize our lives in the near future. Already, companies such as Google, Uber, Nutonomy, Volvo, are deploying SDCs on roads, and have shown that SDCs are almost ready for production use. Many Canadian provinces have already passed laws allowing the use of SDCs on public roads, e.g., Ontario. Experts have predicted the large-scale adoption of SDCs within the next 5 to 10 years. SDCs offer many societal benefits such as drastically reduce the number of accidents resulting in loss of life and property, and make driving safer. SDCs today rely upon complex algorithms executing on specialized silicon chips for their key tasks such as pedestrian detection. Any error in either the software or the hardware can adversely affect the safety of the car. Unfortunately, hardware is becoming less and less reliable due to the scaling of silicon devices to smaller sizes, which while aiding performance, has made them much more susceptible to particle strikes and manufacturing defects. Unlike software faults, faults in the hardware can arise unpredictably and at random locations, even if the software has been well tested. Thus, they cannot be eliminated at design time. Further, they can lead to devastating consequences as software is often unprepared to deal with hardware faults. Therefore, there is a compelling need to make the computer chips in SDCs reliable and to ensure that hardware faults do not lead to safety compromises in SDCs. This proposal will investigate both software and hardware techniques for ensuring the reliability of the systems deployed in SDCs. The main idea is to innovatively co-design the hardware and software deployed in SDCs to leverage the intrinsic resilience afforded by software, design the hardware to provide tunable reliability, and explore innovative software algorithms that are capable of masking or tolerating hardware faults. We will also take into account the power consumption of the chip, and jointly optimize both power and reliability.