Heterogeneous manycore accelerator architectures

最近半导体技术规模的中断导致了在单个硅芯片上集成许多计算“核心”的系统的广泛发展。随着每芯片核心数的增加，对一些核心进行专门化变得很重要，当与不断增加的并行度结合在一起时，这将使这些系统的有效编程成为一个挑战。这类系统的例子包括集成了数百个可通过C/C++编程语言扩展进行编程的简单核心的现代图形处理器(GPU)，以及集成了常规(CPU)计算核心和类似于GPU的加速器核心的AMD Fusion微处理器。 该研究计划的目标是探索能够以较低成本提供更高计算性能的新型硬件体系结构，同时简化软件开发过程。该计划包括两条综合的调查路线。第一个重点是新型并行芯片微结构，第二个重点是开发分析建模技术，以快速预测这些体系结构上的应用程序的性能。 我们在第一条线索中的假设是，并行软件开发可以通过新颖的体系结构得到简化，这些体系结构弥合了目前在高端台式机和服务器计算机中对高单线程性能的支持与在当前图形处理器(GPU)中对极限量并行的支持之间存在的鸿沟。我们在第二条问题中的假设是，随着我们达到半导体扩展的极限，性能调优将消耗越来越多的软件开发人员时间，开发人员的工作可以通过使用分析建模来确定性能瓶颈来减轻。 加拿大将从这项研究中受益，因为它减少了计算硬件和软件的开发费用，并通过引领不同种类的并行硬件系统的创新加强了它在全球信息技术产业中的存在。

Recent discontinuities in semiconductor technology scaling have led to the widespread development of systems with many computing "cores" integrated on a single silicon chip. As cores per chip increase it becomes important for some of the cores to be specialized, which when combined with increasing parallelism will make effective programming of these systems a challenge. Examples of such systems include contemporary graphics processors (GPUs) integrating hundreds of simple cores programmable via extensions to the C/C++ programming languages and the AMD Fusion microprocessor that integrates regular (CPU) computing cores with GPU-like accelerator cores. The objective of this research program is to explore novel hardware architectures that deliver higher computing performance at lower cost while simultaneously simplifying the software development process. The program comprises two integrated lines of inquiry. The first focuses on novel parallel chip microachitectures and the the second focuses on developing analytical modeling techniques for rapidly predicting the performance of applications on these architectures. Our hypothesis in the first line of inquiry is parallel software development can be simplified via novel architectures that bridge the chasm that currently exists between support for high single thread performance as found in high end desktop and server computers and the support for extreme amounts of parallelism found in current graphics processors (GPUs). Our hypothesis in the second line of inquiry is performance tuning will consume a growing proportion of software developer time as we reach the limits of semiconductor scaling and developer effort can be mitigated by using analytical modeling to identify performance bottlenecks. Canada stands to benefit from this research through a reduction in computing hardware and software development costs and by strengthening its presence in the global information technology industry by leading in innovation of heterogeneous parallel hardware systems.