Heterogeneous manycore accelerator architectures

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Recent discontinuities in semiconductor technology scaling have led to the widespread development of systems with many computing "cores" integrated on a single silicon chip. As cores per chip increase it becomes important for some of the cores to be specialized, which when combined with increasing parallelism will make effective programming of these systems a challenge. Examples of such systems include contemporary graphics processors (GPUs) integrating hundreds of simple cores programmable via extensions to the C/C++ programming languages and the AMD Fusion microprocessor that integrates regular (CPU) computing cores with GPU-like accelerator cores. The objective of this research program is to explore novel hardware architectures that deliver higher computing performance at lower cost while simultaneously simplifying the software development process. The program comprises two integrated lines of inquiry. The first focuses on novel parallel chip microachitectures and the the second focuses on developing analytical modeling techniques for rapidly predicting the performance of applications on these architectures. Our hypothesis in the first line of inquiry is parallel software development can be simplified via novel architectures that bridge the chasm that currently exists between support for high single thread performance as found in high end desktop and server computers and the support for extreme amounts of parallelism found in current graphics processors (GPUs). Our hypothesis in the second line of inquiry is performance tuning will consume a growing proportion of software developer time as we reach the limits of semiconductor scaling and developer effort can be mitigated by using analytical modeling to identify performance bottlenecks. Canada stands to benefit from this research through a reduction in computing hardware and software development costs and by strengthening its presence in the global information technology industry by leading in innovation of heterogeneous parallel hardware systems.