Nano-templated III-Vs on silicon for silicon photonics

在Si(100)衬底上直接异质外延生长III-V发光材料可以为集成硅光子学(SiP)提供明显的解决方案。然而，硅与典型的III-V材料之间的大的晶格常数失配使得这一过程非常具有挑战性。目前的方法使用切割错误的基板，这与行业标准的cmos工艺不兼容。此外，降低位错密度所需的厚缓冲层损害了增益区和底层硅波导结构之间的光耦合。我们的目标有两个：(A)展示一种使用纳米模板“成核层”技术在Si(100)上直接生长III-V材料的合适方法，以及(B)展示建立在成核层结构上的高质量结构，使得III-V增益区位于靠近Si衬底平面的位置。这种技术将提供全晶片规模的有源光子学，并在硅(100)上实现出色的低损耗光耦合，以实现与现有CMOS工艺兼容的经济单片集成。为了优化结构的设计，将建立增益区和底层硅波导结构之间的光学耦合的数值模型。如果我们能够成功地为我们的合作伙伴思科开发这项技术，它将使他们能够大幅降低数据通信系统的成本，并为加拿大这里的就业和财富创造带来深远的潜在好处。

Direct hetero-epitaxial growth of III-V light emitting materials on Si (100) can provide the obvious solution to integrated Si photonics (SiP). However, the large lattice constant mismatch between Si and typical III-V materials make this process very challenging. Current approaches use miscut substrates, which are incompatible with industry standard CMOS processes. Moreover the thick buffer required to decrease dislocation density compromises optical coupling between the gain region and underlying Si waveguide structures. Our objectives are two-fold: (a) to demonstrate a suitable approach for growing III-V materials directly on Si (100) using nanoscale template "nucleation layer" technology, and (b) demonstrate high quality structures built on the nucleation layer structures, such that the III-V gain region lies proximate to the Si substrate plane. Such technology would provide full wafer-scale active photonics, with excellent low loss optical coupling implemented on Si (100), to enable an economical monolithic integration compatible with existing CMOS technology. Numerical models for optical coupling between the gain region and underlying Si waveguide structures will be developed to optimize the design of structures. If we can successfully develop this technology for our partner CISCO, it will enable them to dramatically reduce costs for datacomm systems and have a profound potential benefit for job and wealth creation here in Canada.