Modeling and Simulation of Deterministic and Stochastic Nano systems

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The relentless downscaling drive in the integrated Very Large Scale Integration (VLSI) circuit technology (from the deep submicron and down to the nano-scale level) has increased the level of challenges in predicting the system performance or estimating its basic figures-of-merit. The main reason for that difficulty stems from the increasing uncertainty that surrounds the actual (i.e., post Silicon-layout) values of the design parameters. Design parameters, in this context, refer to a wide range of circuit design parameters including geometrical and structural parameters, process parameters or electrical parameters. Traditional modeling and simulation approaches have treated those parameters as deterministic variables with well-specified numerical values. However, with the above-mentioned uncertainty surrounding their post-fabrication or actual values, those parameters must be regarded as random variables that are characterized with certain probability density functions (PDF), such as Gaussian or Uniform PDF. With this new development, system performance metrics are no longer deterministic functions in its design parameters, but need to be treated as stochastic processes whose full characterization can be best approached through calculating their PDFs. This goal of computing the PDF of a system is generally known in the mathematical literature as Uncertainty Quantification (UQ).***The proposed research program presented by the applicant will tackle the UQ problem on three different fronts. The first front explores specific areas where this problem has a direct impact on the design methodologies and the cost of design iteration. ***On the second front, advanced approaches based on recently discovered mathematical formulation will be investigated and generalized for reducing the computational cost that arises in the problem of UQ. The third front will focus on developing novel methodologies to take advantage of utilizing alternative computation platforms based on massive parallel architectures that are offered by modern General Purpose Graphical Processing Units (GPGPUs).***In addition to addressing the problem of UQ, the proposed research will continue to build on the success of the high-order stable method that the candidate proposed recently for the simulation of VLSI circuits. The new phase of the proposed research in this regard will aim at including the full range of transistor device models at the deep submicron and the nano-scale levels. The main underlying objective in the proposed approach is to develop a fully automated technique to convert device models, to the novel graph-based rooted tree structure that are more suitable for the high-order stable methods. *** **