Modeling and Simulation of Deterministic and Stochastic Nano systems

集成超大规模集成电路（VLSI）技术的不断缩小（从深亚微米到纳米级）增加了预测系统性能或估计其基本性能指标的挑战。这种困难的主要原因源于围绕设计参数的实际（即后硅布局）值的不确定性的增加。在这种情况下，设计参数是指广泛的电路设计参数，包括几何和结构参数、工艺参数或电气参数。传统的建模和仿真方法将这些参数视为具有明确数值的确定性变量。然而，由于这些参数的后期或实际值存在上述不确定性，因此必须将这些参数视为具有一定概率密度函数（PDF）特征的随机变量，例如高斯或均匀PDF。随着这一新的发展，系统性能指标不再是其设计参数中的确定性函数，而是需要被视为随机过程，其完整表征可以通过计算其pdf来最好地接近。计算系统PDF的目标在数学文献中通常称为不确定性量化（UQ）。

The relentless downscaling drive in the integrated Very Large Scale Integration (VLSI) circuit technology (from the deep submicron and down to the nano-scale level) has increased the level of challenges in predicting the system performance or estimating its basic figures-of-merit. The main reason for that difficulty stems from the increasing uncertainty that surrounds the actual (i.e., post Silicon-layout) values of the design parameters. Design parameters, in this context, refer to a wide range of circuit design parameters including geometrical and structural parameters, process parameters or electrical parameters. Traditional modeling and simulation approaches have treated those parameters as deterministic variables with well-specified numerical values. However, with the above-mentioned uncertainty surrounding their post-fabrication or actual values, those parameters must be regarded as random variables that are characterized with certain probability density functions (PDF), such as Gaussian or Uniform PDF. With this new development, system performance metrics are no longer deterministic functions in its design parameters, but need to be treated as stochastic processes whose full characterization can be best approached through calculating their PDFs. This goal of computing the PDF of a system is generally known in the mathematical literature as Uncertainty Quantification (UQ). The proposed research program presented by the applicant will tackle the UQ problem on three different fronts. The first front explores specific areas where this problem has a direct impact on the design methodologies and the cost of design iteration. On the second front, advanced approaches based on recently discovered mathematical formulation will be investigated and generalized for reducing the computational cost that arises in the problem of UQ. The third front will focus on developing novel methodologies to take advantage of utilizing alternative computation platforms based on massive parallel architectures that are offered by modern General Purpose Graphical Processing Units (GPGPUs). In addition to addressing the problem of UQ, the proposed research will continue to build on the success of the high-order stable method that the candidate proposed recently for the simulation of VLSI circuits. The new phase of the proposed research in this regard will aim at including the full range of transistor device models at the deep submicron and the nano-scale levels. The main underlying objective in the proposed approach is to develop a fully automated technique to convert device models, to the novel graph-based rooted tree structure that are more suitable for the high-order stable methods.