Modeling and Simulation of Deterministic and Stochastic Nano systems

在集成的超大规模集成电路（VLSI）技术中的无情的缩小尺寸驱动（从深亚微米到纳米级）增加了预测系统性能或估计其基本品质因数的挑战水平。造成这一困难的主要原因是围绕实际情况的不确定性越来越大（即，后硅布局）值的设计参数。在此上下文中，设计参数是指广泛的电路设计参数，包括几何和结构参数、工艺参数或电参数。传统的建模和仿真方法将这些参数视为具有明确数值的确定性变量。然而，由于围绕其制造后或实际值的上述不确定性，这些参数必须被视为以某些概率密度函数（PDF）（诸如高斯或均匀PDF）表征的随机变量。随着这一新的发展，系统性能指标不再是确定性的功能，在其设计参数，但需要被视为随机过程，其完整的表征，可以通过计算其PDF最好接近。这种计算系统PDF的目标在数学文献中通常称为不确定性量化（UQ）。 申请人提出的拟议研究计划将从三个不同方面解决UQ问题。第一个方面探讨了这个问题对设计方法和设计迭代成本有直接影响的特定领域。 在第二个方面，先进的方法，最近发现的数学公式的基础上，将进行调查和推广，以减少计算成本中出现的问题UQ。第三条战线将专注于开发新的方法，以利用基于现代通用图形处理单元（GPGPU）提供的大规模并行架构的替代计算平台。 除了解决UQ的问题，拟议的研究将继续建立在高阶稳定的方法，候选人最近提出的VLSI电路的模拟的成功。在这方面，拟议研究的新阶段将旨在包括深亚微米和纳米级的全系列晶体管器件模型。在所提出的方法的主要潜在目标是开发一个完全自动化的技术转换设备模型，新的基于图形的有根树结构，更适合于高阶稳定的方法。

The relentless downscaling drive in the integrated Very Large Scale Integration (VLSI) circuit technology (from the deep submicron and down to the nano-scale level) has increased the level of challenges in predicting the system performance or estimating its basic figures-of-merit. The main reason for that difficulty stems from the increasing uncertainty that surrounds the actual (i.e., post Silicon-layout) values of the design parameters. Design parameters, in this context, refer to a wide range of circuit design parameters including geometrical and structural parameters, process parameters or electrical parameters. Traditional modeling and simulation approaches have treated those parameters as deterministic variables with well-specified numerical values. However, with the above-mentioned uncertainty surrounding their post-fabrication or actual values, those parameters must be regarded as random variables that are characterized with certain probability density functions (PDF), such as Gaussian or Uniform PDF. With this new development, system performance metrics are no longer deterministic functions in its design parameters, but need to be treated as stochastic processes whose full characterization can be best approached through calculating their PDFs. This goal of computing the PDF of a system is generally known in the mathematical literature as Uncertainty Quantification (UQ). The proposed research program presented by the applicant will tackle the UQ problem on three different fronts. The first front explores specific areas where this problem has a direct impact on the design methodologies and the cost of design iteration. On the second front, advanced approaches based on recently discovered mathematical formulation will be investigated and generalized for reducing the computational cost that arises in the problem of UQ. The third front will focus on developing novel methodologies to take advantage of utilizing alternative computation platforms based on massive parallel architectures that are offered by modern General Purpose Graphical Processing Units (GPGPUs). In addition to addressing the problem of UQ, the proposed research will continue to build on the success of the high-order stable method that the candidate proposed recently for the simulation of VLSI circuits. The new phase of the proposed research in this regard will aim at including the full range of transistor device models at the deep submicron and the nano-scale levels. The main underlying objective in the proposed approach is to develop a fully automated technique to convert device models, to the novel graph-based rooted tree structure that are more suitable for the high-order stable methods.