Modeling and Simulation of Deterministic and Stochastic Nano systems

集成超大规模集成电路(VLSI)电路技术(从深亚微米到纳米级)的不断缩小增加了预测系统性能或估计其基本优值的挑战水平。造成这一困难的主要原因是围绕设计参数的实际(即，硅布局后)值的不确定性增加。在本文中，设计参数指的是广泛的电路设计参数，包括几何和结构参数、工艺参数或电气参数。传统的建模和仿真方法将这些参数视为具有明确数值的确定性变量。然而，由于上述参数制造后或实际值的不确定性，这些参数必须被视为具有一定概率密度函数(PDF)特征的随机变量，如高斯或均匀概率密度函数。随着这一新的发展，系统性能指标在其设计参数中不再是确定性函数，而需要被视为随机过程，其完全特征可以通过计算其PDF来最好地逼近。这个计算系统PDF的目标在数学文献中通常被称为不确定性量化(UQ)。 申请者提出的拟议研究计划将从三个不同的方面解决UQ问题。第一个方面探讨了这个问题直接影响设计方法和设计迭代成本的特定领域。 在第二方面，将研究和推广基于最近发现的数学公式的先进方法，以减少在UQ问题中出现的计算成本。第三方面将侧重于开发新的方法，以利用基于现代通用图形处理单元(GPGPU)提供的大规模并行体系结构的替代计算平台。 除了解决UQ问题，拟议的研究将继续建立在候选人最近提出的用于模拟VLSI电路的高阶稳定方法的成功基础上。在这方面拟议研究的新阶段将致力于包括深亚微米和纳米级的各种晶体管器件模型。该方法的主要目标是开发一种完全自动化的技术来将器件模型转换为更适合高阶稳定方法的基于图的有根树结构。

The relentless downscaling drive in the integrated Very Large Scale Integration (VLSI) circuit technology (from the deep submicron and down to the nano-scale level) has increased the level of challenges in predicting the system performance or estimating its basic figures-of-merit. The main reason for that difficulty stems from the increasing uncertainty that surrounds the actual (i.e., post Silicon-layout) values of the design parameters. Design parameters, in this context, refer to a wide range of circuit design parameters including geometrical and structural parameters, process parameters or electrical parameters. Traditional modeling and simulation approaches have treated those parameters as deterministic variables with well-specified numerical values. However, with the above-mentioned uncertainty surrounding their post-fabrication or actual values, those parameters must be regarded as random variables that are characterized with certain probability density functions (PDF), such as Gaussian or Uniform PDF. With this new development, system performance metrics are no longer deterministic functions in its design parameters, but need to be treated as stochastic processes whose full characterization can be best approached through calculating their PDFs. This goal of computing the PDF of a system is generally known in the mathematical literature as Uncertainty Quantification (UQ). The proposed research program presented by the applicant will tackle the UQ problem on three different fronts. The first front explores specific areas where this problem has a direct impact on the design methodologies and the cost of design iteration. On the second front, advanced approaches based on recently discovered mathematical formulation will be investigated and generalized for reducing the computational cost that arises in the problem of UQ. The third front will focus on developing novel methodologies to take advantage of utilizing alternative computation platforms based on massive parallel architectures that are offered by modern General Purpose Graphical Processing Units (GPGPUs). In addition to addressing the problem of UQ, the proposed research will continue to build on the success of the high-order stable method that the candidate proposed recently for the simulation of VLSI circuits. The new phase of the proposed research in this regard will aim at including the full range of transistor device models at the deep submicron and the nano-scale levels. The main underlying objective in the proposed approach is to develop a fully automated technique to convert device models, to the novel graph-based rooted tree structure that are more suitable for the high-order stable methods.