Towards Predictable and Criticality-aware Multi-core Cyber-Physical Systems

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Multi-core platforms such as Multi-Processor System-on-chip (MPSoCs) provide tremendous opportunities for Cyber-Physical Systems (CPS) by providing high-performance and low-cost platforms; however, they come with associated challenges. Advanced CPS execute software components from different vendors, which have different criticalities and requirements. For instance, in the automotive domain, malfunctioning of the Anti-lock Brake System (ABS) has considerably more severe consequences compared to that of the infotainment unit. Accordingly, CPS have to guarantee differential services to applications based on both their criticality and requirements. Service guarantees are problematic in MPSoCs due to the interference on different shared hardware components such as on-chip caches, and off-chip dynamic random access memories (DRAMs). ******Our long-term plan is to enable the deployment of predictable, high-performance CPS using MPSoCs. In the short term, we will investigate approaches to deliver guaranteed service for software components running on MPSoCs to satisfy the requirements of CPS by addressing the interference challenge at different system components including: (1) cache hierarchy, and (2) main memory. We will explore solutions at different system-levels including (1) The operating system level, (2) compiler-level, and (3) hardware-level. For cache hierarchy: We will focus on developing criticality-aware hardware cache coherence protocols to predictably and coherently share data in MPSoCs for mixed-criticality CPS. For the main memory: we will study the usage of different memory types to satisfy the needs of different applications. For instance, DDR DRAMs provide high capacity, Graphics DDRs (GDDRs) provide high bandwidth, while Reduced Latency DRAM (RLDRAM) offers low latency. We promote a heterogeneous combination of these different devices and provide memory controller designs that simultaneously manage them in MPSoCs for CPS. Additionally, we will examine novel operating-system approaches (such as virtual to physical address mapping techniques) as well as compiler-based techniques (such as code transformations) to target the trade-offs among high-performance software components and latency-critical ones. These techniques will remap memory accesses into different memory regions based on the criticality and requirements of all applications. We envision such techniques to modify the timing behavior of applications without changing their functionality such that we meet all the latency and bandwidth requirements of all applications with different criticality levels. ******The proposed research aims at significantly contributing to the design methodologies of high-performance, time-critical CPS. CPS is a strategic area, in which Canada has to be in the forefront through fundamental research such as this proposal. ***In addition, this proposal has a wide impact on several critical markets including: IoT, automotive, and avionics.