Towards Predictable and Criticality-aware Multi-core Cyber-Physical Systems

多核平台，如多处理器片上系统(MPSoC)，通过提供高性能和低成本的平台，为网络物理系统(CP)提供了巨大的机遇，但它们也伴随着相关的挑战。高级CP执行来自不同供应商的软件组件，这些组件具有不同的关键程度和要求。例如，在汽车领域，防抱死制动系统(ABS)的故障与信息娱乐单元的故障相比，其后果要严重得多。因此，CP必须根据应用程序的关键程度和要求来保证不同的服务。由于片上高速缓存和片外动态随机存取存储器(DRAM)等不同共享硬件组件上的干扰，MPSoC中的服务保证是有问题的。我们的长期计划是使用MPSoC部署可预测的高性能CP。在短期内，我们将研究通过解决不同系统组件的干扰挑战来为运行在MPSoC上的软件组件提供有保证的服务的方法，包括：(1)高速缓存层次结构和(2)主存。我们将探索不同系统级别的解决方案，包括(1)操作系统级别、(2)编译器级别和(3)硬件级别。对于高速缓存层次结构：我们将专注于开发关键程度感知的硬件高速缓存一致性协议，以便在MPSoC中针对混合关键程度CP可预测且一致地共享数据。对于主存：我们将研究不同内存类型的使用，以满足不同应用的需求。例如，DDR DRAM提供高容量，图形DDR(GDDR)提供高带宽，而降低延迟DRAM(RLDRAM)提供低延迟。我们促进了这些不同设备的异类组合，并为CP提供了在MPSoC中同时管理它们的内存控制器设计。此外，我们将研究新的操作系统方法(如虚拟到物理地址映射技术)以及基于编译器的技术(如代码转换)，以平衡高性能软件组件和延迟关键型软件组件之间的权衡。这些技术将根据所有应用程序的关键程度和要求将内存访问重新映射到不同的内存区域。我们设想这样的技术可以在不更改应用程序功能的情况下修改应用程序的计时行为，从而满足具有不同关键程度的所有应用程序的所有延迟和带宽要求。这项拟议的研究旨在为高性能、时间关键型CPS的设计方法做出重大贡献。CPS是一个战略领域，加拿大必须通过这项提议等基础研究走在前列。此外，该提案还对几个关键市场产生了广泛影响，包括：物联网、汽车和航空电子设备。

Multi-core platforms such as Multi-Processor System-on-chip (MPSoCs) provide tremendous opportunities for Cyber-Physical Systems (CPS) by providing high-performance and low-cost platforms; however, they come with associated challenges. Advanced CPS execute software components from different vendors, which have different criticalities and requirements. For instance, in the automotive domain, malfunctioning of the Anti-lock Brake System (ABS) has considerably more severe consequences compared to that of the infotainment unit. Accordingly, CPS have to guarantee differential services to applications based on both their criticality and requirements. Service guarantees are problematic in MPSoCs due to the interference on different shared hardware components such as on-chip caches, and off-chip dynamic random access memories (DRAMs). Our long-term plan is to enable the deployment of predictable, high-performance CPS using MPSoCs. In the short term, we will investigate approaches to deliver guaranteed service for software components running on MPSoCs to satisfy the requirements of CPS by addressing the interference challenge at different system components including: (1) cache hierarchy, and (2) main memory. We will explore solutions at different system-levels including (1) The operating system level, (2) compiler-level, and (3) hardware-level. For cache hierarchy: We will focus on developing criticality-aware hardware cache coherence protocols to predictably and coherently share data in MPSoCs for mixed-criticality CPS. For the main memory: we will study the usage of different memory types to satisfy the needs of different applications. For instance, DDR DRAMs provide high capacity, Graphics DDRs (GDDRs) provide high bandwidth, while Reduced Latency DRAM (RLDRAM) offers low latency. We promote a heterogeneous combination of these different devices and provide memory controller designs that simultaneously manage them in MPSoCs for CPS. Additionally, we will examine novel operating-system approaches (such as virtual to physical address mapping techniques) as well as compiler-based techniques (such as code transformations) to target the trade-offs among high-performance software components and latency-critical ones. These techniques will remap memory accesses into different memory regions based on the criticality and requirements of all applications. We envision such techniques to modify the timing behavior of applications without changing their functionality such that we meet all the latency and bandwidth requirements of all applications with different criticality levels. The proposed research aims at significantly contributing to the design methodologies of high-performance, time-critical CPS. CPS is a strategic area, in which Canada has to be in the forefront through fundamental research such as this proposal. In addition, this proposal has a wide impact on several critical markets including: IoT, automotive, and avionics.