Analog power minimization for high-speed 4-PAM serdes

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There is a constant demand for increased data consumption around the world. The internet continues to expand with increased demand for video, social media, and business use. In addition, there are now almost 3 times as many Internet-Of-Things (IOT) devices connected than the world's population. In 2017, there were 20 billion internet connected devices and that number is expected to grow to 75 bil- lion by 2025. With this explosion in internet data usage, there is a constant need for more powerful data centres. Within data centres, there exists storage, servers, switches/hubs and networking gear. All of these components exist within large racks of equipment that require high speed SERDES over backplanes for interconnection and these SERDES need to keep increasing in speed to keep up with demand to move more data (SERDES are high speed communication channels between integrated circuits). While it is possible to keep increasing SERDES data rates, this comes at a cost of much higher power. However, the power dissipation for data centres is of great concern worldwide as it has been predicted that these data centres could consume 20 percent of global electricity by year 2025 and contribute up to 14 percent of global greenhouse emmisions by year 2040. Thus, reducing power in data centres is of critical concern. This project looks at new techniques to reduce power in these very high speed SERDES and therefore can help to reduce the power in future data centres.