Development of radiation tolerant cell libraries and a RISC-V microcontroller with GF 12nm FinFET technology

与思科系统(Cisco)和XIHOS Systems(XIHOS)合作的项目的总体目标是开发采用最先进的GlobalFundries(GF)12 nm FinFET技术制造的容错逻辑电路，以降低合作伙伴电子产品的软错误率。在现代商业硅技术中，现代集成电路(IC)中的晶体管尺寸已经达到纳米级。因此，集成电路变得更容易受到宇宙射线或包装材料产生的高能粒子引起的单粒子效应(参见)的影响，这通常被称为软错误。该项目的主要目标是表征12 nm FinFET工艺中的单粒子效应，并开发/评估冗余逻辑技术以降低数字电路中的软错误率。与体块技术相比，FinFET技术在软误码率和功耗方面表现出了显著的降低，这使得它们在许多工业应用中具有吸引力。这一拟议的协作项目分为两个阶段。在第一阶段，将利用该技术在测试芯片中设计和制造各种容错存储元件，如触发器和逻辑门。还将开发耐辐射标准单元库。在第二阶段，将利用容错标准单元库设计容错RISC-V微处理器，以评估其软错误性能。在每个项目阶段，将使用所提出的测试结构来设计测试芯片。离子束(重离子、中子和质子)将用于评估测试结构的性能。调查还将使用校园内的脉冲激光设备来模拟离子撞击。此外，还将利用器件和电路级仿真工具对测试电路的性能进行建模和表征。这项研究将使我们的工业合作伙伴能够使用具有成本效益的技术优势(低功耗、高速度等)。在不影响可靠性和性能的情况下，实现了纳米级cmos技术。两名博士、一名硕士、一名本科生和一名博士后将在这个项目中接受培训，并制作硅可靠性领域的出版物。

The overall objectives of the collaborative project with Cisco Systems (Cisco) and Xiphos Systems (Xihos) are to develop fault-tolerant logic circuits fabricated with the most advanced Globalfundries (GF) 12nm FinFET technologies in order to reduce the soft error rate in partners' electronic products. The size of transistors in the modern integrated circuits (ICs) has been scaled to the nanometer range in modern commercial silicon technologies. As a result, ICs have become more vulnerable to single event effects (SEE) induced by energetic particles from either cosmic rays or packaging materials, which are normally referred to as soft errors. The project's main objectives are to characterize the single event effects in the 12nm FinFET process and develop/evaluate the redundant logic techniques to reduce the soft error rates in digital circuits. FinFET technologies have shown substantial reduction in soft error rate and power compared to bulk technologies, which makes them attractive in many industrial applications. There are two phases in this proposed collaborative project. In the first phase, various fault-tolerant storage components like flip-flops and logic gates will be designed and fabricated in a test chip with this technology. A radiation-tolerant standard cell library will also be developed. In the second phase, a fault-tolerant RISC-V microprocessor will be designed with the fault-tolerant standard cell library to evaluate their soft error performance. In each project phase, a test chip will be designed with the proposed test structures. Ion beams (heavy ions, neutron, and protons) will be used to evaluate the test structures' performance. The investigation will also use an on-campus pulsed laser facility to simulate the ion hits. In addition, device and circuit-level simulation tools will be utilized to model and characterize the test circuits' performance. The research will enable our industrial partner using the cost-effective technologies with the advantages (lower power, higher speed, etc.) of nanoscale CMOS technologies without compromising reliability and performance. Two PhD, one M.Sc, one undergraduate student and one postdoc fellow will be trained in this project alone with producing publications in the silicon reliability field.