Radiation-Tolerant Microelectronics for Space and Commercial Applicaitons

硅技术已经成为工业中大多数电子设备的主导平台。硅工艺的规模化显著提高了集成电路(IC)的性能。然而，由于器件尺寸小，工作电压低，纳米级集成电路对工作干扰变得高度敏感。这些干扰，特别是由集成电路中含能粒子引起的单粒子效应(SEE)引起的干扰，可能会在逻辑电路节点中引入瞬时脉冲或扰乱存储单元中的数据。它们的影响范围从单一数据损坏到严重的系统崩溃。例如，由于宇宙粒子造成的突然而神秘的崩溃，太阳微系统公司在2000年被迫召回其旗舰服务器。即使是在地面环境中的集成电路，由声表面波引起的错误率也可能比器件磨损等硬故障引起的错误率高出100倍。拟议研究计划的目标是研究微电子学中的SEE，并进一步提出具有成本效益的缓解解决方案，以实现电子电路和系统的可靠运行。采用SEE硬化技术的各种逻辑电路和系统将在使用先进硅技术的测试芯片中设计和制造。离子束(质子和重离子)将被用来评估它们在SEE耐受性方面的性能。已经建立了一个在校脉冲激光设施，并将作为一种调查工具来表征测试芯片中的SEE，因为它可以在指定的位置和时间精确地在IC中诱导SEE。此外，还将使用器件级和电路级仿真工具对测试电路的性能进行建模和表征。模拟结果将被用来与激光和离子辐射结果相关联，这将提供关于集成电路中SEE的洞察、理解和信息。拟议的计划将为加拿大工业开发SEE容错技术，以提高微电子产品的可靠性。该计划将为一批高技能人员提供进入这一创新研究领域所需的培训。

Silicon technologies have been the dominant platform for the majority of the electronic devices in industry. The silicon technology scaling has significantly improved the performance of integrated circuits (ICs). However, due to the small device dimension and low operating voltages, nanoscale ICs have become highly sensitive to operational disturbances. These disturbances, especially those caused by single event effects (SEEs) due to energetic particles in ICs, can introduce transient pulses in logic circuit nodes or upset data in storage cells. Their impact can range from a single data corruption to a severe system crash. For example, Sun Microsystems were forced to recall their flagship servers in 2000 due to sudden and mysterious crashes caused by cosmic particles. Even for ICs in terrestrial environments, the error rates caused by SEEs can be 100 times higher than those from hard failures such as device wear out. The objectives of the proposed research program are to study the SEEs in microelectronics and, further, advise cost-effective mitigation solutions to achieve reliable operations for electronic circuits and systems. Various logic circuits and systems with SEE-hardening techniques will be designed and fabricated in test chips using advanced silicon technologies. Ion beams (protons and heavy ions) will be used to evaluate their performance in the context of SEE tolerance. An on-campus pulsed laser facility has been established and will be used as an investigation tool to characterize SEEs in the test chips, as it can precisely induce SEEs in the ICs at a designated location and time. In addition, device- and circuit-level simulation tools will be used to model and characterize the performance of the test circuits. The simulation results will be used to correlate with the laser and ion radiation results, which will provide insight, understanding and information about SEEs in ICs. The proposed program will develop SEE-tolerant technologies for the Canadian industry in order to improve the reliability of microelectronics. This program will equip a number of highly skilled personnel with the training necessary to enter this innovative field of research.