Radiation-Tolerant Microelectronics for Space and Commercial Applicaitons

硅技术已经成为工业中大多数电子设备的主导平台。硅技术的规模化极大地提高了集成电路的性能。然而，由于器件尺寸小，工作电压低，纳米级集成电路对工作干扰非常敏感。这些干扰，特别是由集成电路中的高能粒子引起的单事件效应（SEEs）引起的干扰，可以在逻辑电路节点中引入瞬态脉冲或扰乱存储单元中的数据。它们的影响范围从单个数据损坏到严重的系统崩溃。例如，由于宇宙粒子引起的突然而神秘的崩溃，Sun Microsystems在2000年被迫召回其旗舰服务器。即使对于地面环境中的集成电路，see引起的错误率也可能比设备磨损等硬故障造成的错误率高100倍。拟议的研究计划的目标是研究微电子中的see，并进一步提出具有成本效益的缓解解决方案，以实现电子电路和系统的可靠运行。各种逻辑电路和系统与see硬化技术将设计和制造测试芯片使用先进的硅技术。离子束（质子和重离子）将用于评估它们在SEE耐受性背景下的性能。校园内的脉冲激光设备已经建立，并将作为一种调查工具来表征测试芯片中的see，因为它可以在指定的地点和时间精确地诱导ic中的see。此外，器件和电路级仿真工具将用于模拟和表征测试电路的性能。模拟结果将用于与激光和离子辐射结果的关联，这将提供有关集成电路中see的见解，理解和信息。该计划将为加拿大工业开发耐see技术，以提高微电子的可靠性。该计划将为一些高技能人才提供进入这一创新研究领域所需的培训。

Silicon technologies have been the dominant platform for the majority of the electronic devices in industry. The silicon technology scaling has significantly improved the performance of integrated circuits (ICs). However, due to the small device dimension and low operating voltages, nanoscale ICs have become highly sensitive to operational disturbances. These disturbances, especially those caused by single event effects (SEEs) due to energetic particles in ICs, can introduce transient pulses in logic circuit nodes or upset data in storage cells. Their impact can range from a single data corruption to a severe system crash. For example, Sun Microsystems were forced to recall their flagship servers in 2000 due to sudden and mysterious crashes caused by cosmic particles. Even for ICs in terrestrial environments, the error rates caused by SEEs can be 100 times higher than those from hard failures such as device wear out. The objectives of the proposed research program are to study the SEEs in microelectronics and, further, advise cost-effective mitigation solutions to achieve reliable operations for electronic circuits and systems. Various logic circuits and systems with SEE-hardening techniques will be designed and fabricated in test chips using advanced silicon technologies. Ion beams (protons and heavy ions) will be used to evaluate their performance in the context of SEE tolerance. An on-campus pulsed laser facility has been established and will be used as an investigation tool to characterize SEEs in the test chips, as it can precisely induce SEEs in the ICs at a designated location and time. In addition, device- and circuit-level simulation tools will be used to model and characterize the performance of the test circuits. The simulation results will be used to correlate with the laser and ion radiation results, which will provide insight, understanding and information about SEEs in ICs. The proposed program will develop SEE-tolerant technologies for the Canadian industry in order to improve the reliability of microelectronics. This program will equip a number of highly skilled personnel with the training necessary to enter this innovative field of research.