Predictable Multicore System-on-Chips for Automotive Safety-critical Systems

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Automotive vehicles play a vital role in our lives. They provide one of the most common modes of transportation for millions of people. Today's automotive vehicles are a mix of mechanical and computing components where the computing components provide features such as advanced driver assistance systems and infotainment. Over the years, the number of computing components in a vehicle has grown and this trend is expected to continue accelerating with fully autonomous vehicles on the horizon. Safety in automotive vehicles is paramount because a failure in execution may result in significant injury or loss of lives. Thus, it is imperative that the application's execution is both functionally correct and guaranteed to be temporally within the bounds established by the application. For example, a delay in braking may have catastrophic consequences. This makes automotive vehicles an example of a safety-critical system. A central tenet in designing automotive vehicles is ensuring that they are certified. For example, ISO-26262 is a standard for automotive safety-critical systems (ASCSs). Certification includes processes that ensure the functionality is correct, and that the temporal behaviour of the application is within pre-determined deadlines. Providing assurances that an execution never exceeds a deadline is extremely challenging. This is because the underlying computing components lack timing predictability. That is, it is difficult to determine how long an application would take to execute in the worst case. This difficulty is attributed to the design of the computing components and their integration to form a system-on-chip (SoC). For example, current SoCs in ASCSs are complex with multiple cores, shared memories, and custom hardware. It is not surprising that they lack timing predictability. Nonetheless, such SoCs are highly coveted as they significantly reduce costs, improve performance, and are energy efficient. The overarching goal of my research program is to design predictable and high performance heterogeneous multicore SoCs for ASCSs. This proposal has five research objectives: (1) investigate predictable cache coherence mechanisms with practical memory hierarchies and scalable directory-based protocols; (2) design predictable and coherent data communication mechanisms across heterogeneous computing elements; (3) develop programming language extensions to annotate properties of data sharing useful for worst-case analyses; (4) develop predictable virtualization for ASCS; and, (5) implement a prototype. The results from this research will have long-lasting impact on both the Canadian economy and society. Industries of varying sizes will be able to evaluate the proposed techniques, and potentially adopt them into their products. The results may spawn innovative industries that, for example, may focus on providing customized solutions such as real-time operating systems specifically designed to support predictable multicore SoCs.