Collaborative Research: SHF: MEDIUM: Smart Integrated Tuning of Parallel Code for Multicore and Manycore Systems

合作研究：SHF：MEDIUM：多核和众核系统并行代码的智能集成调整

• 批准号: 2211983
• 负责人: Barbara Chapman
• 金额: $ 24.39万
• 依托单位: SUNY at Stony Brook
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-10-01 至 2026-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2211983&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; MEDIUM; Smart

High Performance Computing (HPC) entails executing code on multicore and manycore architectures. To better utilize multicore/manycore architectures, parallel programming models have emerged. But often using these parallel models naively will not be able to scratch the surface of the potential performance gains such systems can provide. A common technique for improving performance is to add more hardware resources. However, this is expensive and system integration is usually an onerous task. To this end, the investigators propose a framework of improving performance by better utilization of the available resource and identifying near-optimal configuration. These configurations can take the form of code optimizations, as well as intelligent resource mapping and utilization. Specifically, this project is concerned with identifying code optimizations and runtime configurations that can potentially speed up executions manifold. Faster executions can also implicitly lead to reduced power consumption. Additionally, for situations where existing execution performance is acceptable, the proposed approach can also be extended to optimize for other performance metrics such as power. Power consumption is usually a huge bottleneck for HPC systems, and is a source of concern for organizations that deploy such systems; these concerns are both fiscal and environmental. The investigators posit that the framework outlined in this project can also be extended to optimize for power consumption without compromising execution performance.The investigators’ aim is to provide such an AI-assisted framework that can automatically configure parallel code considering the underlying hardware architecture. The steps necessary to build such a framework lie at the convergence of compiler technologies, performance analysis and modeling, and deep learning. A primary driver of this project will be developing a program representation technique targeted towards parallel code. Existing representations target mostly serial code and cannot fully encapsulate the interactions and complexities of parallel code. Such a code representation technique is highly suited to analyses using deep learning. A means of representing parallel code in a machine learning friendly format will be very beneficial to the overall program analysis community. The proposed code representation will take the form of a graph, in order to correctly typify the inherent structure present in code. The investigators propose modeling this code representation using state-of-the-art Graph Neural Network (GNN) techniques. The modeled embeddings will be used in conjunction with task specific features in order to identify near optimum configurations for improved performance. The overall scale of this project will span the entire “source code to execution” pipeline that most HPC workloads follow. The aim of this project is to optimize each optimizable step in the pipeline. A sample optimization pipeline can take the following form: given a parallel code, our GNN-based code optimization model will predict the best optimizations for the given code, followed by identifying the best device (CPU, GPU, and others) for executing the optimized code. Further downstream, our framework will identify the optimum runtime configurations appropriate for the device under consideration. The ideas presented in this project can have the potential effect of increased hardware utilization and reduced future hardware commissioning.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

高性能计算（HPC）需要在多核和众核架构上执行代码。为了更好地利用多核/众核架构，出现了并行编程模型。但是，通常天真地使用这些并行模型将无法触及此类系统可以提供的潜在性能增益的表面。提高性能的一种常用技术是添加更多的硬件资源。然而，这是昂贵的，系统集成通常是一项繁重的任务。为此，研究人员提出了一个框架，通过更好地利用可用资源和确定接近最佳的配置来提高性能。这些配置可以采取代码优化以及智能资源映射和利用的形式。具体来说，这个项目关注的是识别代码优化和运行时配置，这些配置可能会加速执行。更快的执行也可以隐含地导致降低功耗。此外，对于现有的执行性能是可接受的情况下，所提出的方法也可以扩展到优化其他性能指标，如功率。功耗通常是HPC系统的一个巨大瓶颈，也是部署此类系统的组织关注的问题;这些问题既有财政问题，也有环境问题。研究人员表示，该项目中概述的框架还可以扩展，以优化功耗而不影响执行性能。研究人员的目标是提供这样一个AI辅助框架，可以根据底层硬件架构自动配置并行代码。构建这样一个框架所需的步骤在于编译器技术、性能分析和建模以及深度学习的融合。该项目的主要驱动因素将是开发针对并行代码的程序表示技术。现有的表示主要针对串行代码，不能完全封装并行代码的交互和复杂性。这种代码表示技术非常适合使用深度学习进行分析。以机器学习友好格式表示并行代码的方法将对整个程序分析社区非常有益。所提出的代码表示将采用图形的形式，以便正确地代表代码中存在的固有结构。研究人员建议使用最先进的图神经网络（GNN）技术对这种代码表示进行建模。模型化的嵌入将与任务特定的功能结合使用，以确定接近最佳的配置，以提高性能。该项目的总体规模将跨越大多数HPC工作负载遵循的整个“源代码到执行”管道。该项目的目的是优化管道中的每个可优化步骤。示例优化管道可以采取以下形式：给定并行代码，我们基于GNN的代码优化模型将预测给定代码的最佳优化，然后确定执行优化代码的最佳设备（CPU，GPU等）。进一步下游，我们的框架将确定最佳的运行时配置适合所考虑的设备。该项目中提出的想法可能会增加硬件利用率并减少未来的硬件调试。该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。