Circuits and Architecture Innovations for Beyond CMOS Scaling

超越 CMOS 缩放比例的电路和架构创新

• 批准号: RGPIN-2020-06828
• 负责人: Sheikholeslami, Ali
• 金额: $ 2.84万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751654
• 关键词: Circuits; Architecture; Innovations; Beyond; CMOS

Circuits and Architecture Innovations for Beyond CMOS Scaling: Over the past few decades, transistor gate length has shrunk from a few micrometers to a few nanometers, allowing nearly a million transistors today to occupy the same area as a single transistor from a few decades ago. This dramatic shrinkage in transistor size has enabled the integration of over a billion transistors on a single chip, and has propelled both the computation performance and the data communication speed that we enjoy today. However, as we approach the atomic distance in gate length, further scaling of transistor sizes has become exceedingly difficult. In fact, it is expected for this scaling to end in the next two generations of CMOS technology at around 2nm gate length. The end to this scaling means we can no longer increase the number of transistors per microchip, nor can we expect an exponential increase in computations and communications. Yet, our desire and need for further increases in speed are far from over. Indeed, many of the challenging problems of our time, such as those in the environment, health, and finance, require much higher computation speed than what will be available at the end of CMOS scaling. This research program will use advanced CMOS technologies to provide further performance improvements in electronics at the system and the architecture levels. At the system level, we design interface circuits to "stitch" several dies together, effectively increasing the number of transistors per chip. These circuits must have a small area and low power overhead so as to leave most of the area and power for the main operation of the larger chip. The expected outcome of this research is a linear increase in the number of transistors beyond the CMOS scaling. Innovations at the architecture level will provide drastic benefits far beyond the end of CMOS scaling. In this research, we will use known algorithms in simulated annealing for optimization, currently implemented in software, and implement them in CMOS. Given the massive parallelism that is available in CMOS, we expect a speedup of at least 3-4 orders of magnitude for solving optimization problems. This level of speedup is expected to disrupt the current software approach and pave the way for solving problems that have never been solved before. These two research directions will be able to provide performance improvements beyond the end of CMOS scaling, providing a bridge to quantum computing.

超越CMOS缩放的电路和架构创新：在过去的几十年里，晶体管栅极长度已经从几微米缩小到几纳米，这使得今天近一百万个晶体管占据了与几十年前一个晶体管相同的面积。晶体管尺寸的急剧缩小使得在单个芯片上集成超过10亿个晶体管成为可能，并推动了我们今天所享受的计算性能和数据通信速度。然而，当我们接近栅极长度的原子距离时，晶体管尺寸的进一步缩放变得极其困难。事实上，预计这种缩放将在未来两代CMOS技术中以2nm栅极长度结束。这种规模的终结意味着我们不能再增加每个微芯片的晶体管数量，我们也不能指望计算和通信的指数级增长。然而，我们对进一步提高速度的渴望和需求远未结束。事实上，我们这个时代的许多具有挑战性的问题，例如环境、健康和金融领域的问题，都需要比CMOS扩展结束时更高的计算速度。该研究计划将使用先进的CMOS技术，在系统和架构级别上进一步提高电子性能。在系统层面，我们设计了接口电路，将几个芯片“缝合”在一起，有效地增加了每个芯片的晶体管数量。这些电路必须具有较小的面积和较低的功率开销，以便将大部分面积和功率留给较大的芯片的主要操作。这项研究的预期结果是晶体管数量的线性增加，超出了CMOS的规模。架构层面的创新将带来巨大的好处，远远超过CMOS扩展的终结。在本研究中，我们将使用已知的模拟退火算法进行优化，目前在软件中实现，并在CMOS中实现。考虑到CMOS中可用的大量并行性，我们期望在解决优化问题时至少有3-4个数量级的加速。这种程度的加速预计将打破当前的软件方法，并为解决以前从未解决过的问题铺平道路。这两个研究方向将能够提供超越CMOS扩展末端的性能改进，为量子计算提供桥梁。