Circuits and Architecture Innovations for Beyond CMOS Scaling

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Circuits and Architecture Innovations for Beyond CMOS Scaling: Over the past few decades, transistor gate length has shrunk from a few micrometers to a few nanometers, allowing nearly a million transistors today to occupy the same area as a single transistor from a few decades ago. This dramatic shrinkage in transistor size has enabled the integration of over a billion transistors on a single chip, and has propelled both the computation performance and the data communication speed that we enjoy today. However, as we approach the atomic distance in gate length, further scaling of transistor sizes has become exceedingly difficult. In fact, it is expected for this scaling to end in the next two generations of CMOS technology at around 2nm gate length. The end to this scaling means we can no longer increase the number of transistors per microchip, nor can we expect an exponential increase in computations and communications. Yet, our desire and need for further increases in speed are far from over. Indeed, many of the challenging problems of our time, such as those in the environment, health, and finance, require much higher computation speed than what will be available at the end of CMOS scaling. This research program will use advanced CMOS technologies to provide further performance improvements in electronics at the system and the architecture levels. At the system level, we design interface circuits to "stitch" several dies together, effectively increasing the number of transistors per chip. These circuits must have a small area and low power overhead so as to leave most of the area and power for the main operation of the larger chip. The expected outcome of this research is a linear increase in the number of transistors beyond the CMOS scaling. Innovations at the architecture level will provide drastic benefits far beyond the end of CMOS scaling. In this research, we will use known algorithms in simulated annealing for optimization, currently implemented in software, and implement them in CMOS. Given the massive parallelism that is available in CMOS, we expect a speedup of at least 3-4 orders of magnitude for solving optimization problems. This level of speedup is expected to disrupt the current software approach and pave the way for solving problems that have never been solved before. These two research directions will be able to provide performance improvements beyond the end of CMOS scaling, providing a bridge to quantum computing.