Transceiver Circuits for Optical Backplanes

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Optical links have long been known as lighter, cleaner, and faster alternatives to copper cables for long-haul data communication where the distance between communicating nodes is in kilometers. In the last decade, however, as the sheer weight and volume of the copper cables have increased substantially, optical links have replaced copper cables in communication over shorter distances, such as a few meters between computers in data centers. Today, optical links are competing against copper at distances as short as a few centimeters, such as those between a microprocessor and a memory on a printer circuit board (PCB), for speeds in excess of 25Gb/s. At these speeds, the copper traces attenuate the electrical signal so much that it is extremely hard to recover the correct data at the receiver end no matter how much electronics one includes at the two ends of the link. On the other hand, the attenuation of an optical channel is known to be negligible at these distances even at far higher data rates. What has prohibited so far the wider use of optical backplanes is mainly the cost of electrical to optical and optical to electrical interfaces and the surrounding electronics to compensate for various imperfections of these interfaces. This is in addition to the assembly cost of the chips on board as much more precise alignments are necessary. This proposal relates to the innovation of designs (devices and circuits) for optical/electrical interfaces, and the electronics surrounding these interfaces. In particular, we propose designs for optical devices such as the ring modulators, photo-detectors, and optical filters, and electronic circuits such as trans-impedance amplifiers (TIA), limiting amplifiers, equalizers, and clock and data recovery circuits. The long-term objective of this research is to demonstrate a fully integrated transceiver for optical backplanes. The short-term objectives are to design, fabricate, and test individual building blocks of the complete transceiver. As part of this research, we also develop a system-level model (in Matlab or Simulink) that includes all the building blocks, along with their main sources of non-idealities. This model will be used to identify the link performance as a function of key design parameters. Accordingly, we determine the sensitivity of the link performance to each design parameter in order to identify the performance limits of the architectures. Once we determine the final architecture, we will move towards implementing one block at a time in circuit level. We will test each block individually before moving on to higher levels of integration.