Design Automation Algorithms for High-Speed Integrated Circuits and Microsystems

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Advances of integrated circuit technology have increased the design complexity and operating signal speeds of electronic devices and are placing significant demands on electronic design automation (EDA) tools to provide the same efficiency and accuracy. Reduced feature sizes, and increasing packing densities and operating frequencies require multidisciplinary design methodologies such as electrical, thermal and electromagnetic analysis to accurately model the signal and power integrity of high-speed circuits. With higher operating frequencies, signal integrity issues such as signal delay, distortion, crosstalk and attenuation dominate and significantly degrade circuit performance. These effects exist throughout the design process at the chip, packaging, printed-circuit-board and backplane levels. In general, distributed circuits are modeled using partial differential equations and when discretized produce large system of equations, which are computationally expensive to solve. Furthermore, due to the increased packing densities of integrated circuits, it is becoming essential to model highly coupled interconnect and power distribution networks with many ports. Consequently, the underlying algorithms of traditional EDA tools have become ineffective and in some cases obsolete in addressing the multidisciplinary nature and computational complexity of modern circuit designs. Currently, high-speed circuits is not modeled appropriately by commercial circuit simulators, and stands as one of the major bottlenecks in the design of integrated circuits. The high-tech electronic and communication industry have become important sectors to the Canadian economy. To remain competitive in global markets, our industries have to design circuits quicker with increased accuracy and functionality. The aim of this research proposal is to develop advanced modeling and simulation algorithms for efficient and accurate analysis and design of high-speed integrated circuits and microsystems. This will be achieved by extending the scope of macromodeling algorithms to efficiently model large multi-port distributed electromagnetic systems in a unified simulation circuit environment. Furthermore, new parallel computing techniques based on waveform relaxation will be developed to reduce the computational complexity of large-scale integrated circuits. The emphasis will be to develop interactive design verification techniques that will enable iterative and repetitive signal and power integrity analysis of large complicated distributed circuits. This will lead to better circuit designs, shorter design cycles and lower costs.