Electronic Design Automation Algorithms for Signal Integrity Analysis of High Speed Integrated Circuits

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With the rapid advances of technology, system complexity and signal speeds, significant demands are placed on Electronic Design Automation (EDA) tools to provide the same efficiency and accuracy. Innovations in fabrication process technology have significantly reduced the feature sizes of integrated circuits and increased packing densities of chips. Aggressive design objectives such as system on chip coupled with increased operating frequencies require multidisciplinary design methodologies such as electrical, thermal and electromagnetic analysis to accurately model the signal and power integrity of high-speed circuits. As frequency increases, interconnects behave like distributed transmission lines and effects such as ringing, signal delay, distortion, attenuation and crosstalk can severely degrade signal integrity. These effects are observed at the chip, packaging, printed-circuit-board and backplane levels. In general, distributed interconnects are modeled using partial differential equations and when discretized produce large system of equations, which are computationally expensive to solve. Furthermore, due to the increased packing densities of integrated circuits, it is becoming essential to model highly coupled interconnect and power distribution networks with many ports. As a result of these technological advancements, the underlying algorithms of traditional EDA tools have become ineffective and in some cases obsolete in addressing the multidisciplinary nature and computational complexity of modern circuit designs. Currently, the design of multi-port distributed networks is not handled appropriately by circuit simulators and stand as one of the major bottlenecks in design in signal and power integrity analysis.** The aim of this research proposal is to develop advanced modeling and simulation algorithms for efficient and accurate analysis and design of high-speed integrated circuits. This will be achieved by extending the scope of macromodeling algorithms to efficiently model large multi-port distributed electromagnetic systems in a unified circuit simulation environment. Furthermore new parallel computing and model order reduction techniques will be developed to reduce the computational complexity of large scale high-speed integrated circuits. The emphasis will be to develop interactive design verification techniques that will enable iterative and repetitive signal and power integrity analysis of large complicated distributed networks. This will lead to better circuit designs, shorter design cycles and lower costs.