CAREER: Re-thinking Electronic Design Automation Algorithms for Secure Outsourced Integrated Circuit Fabrication

半导体芯片制造正越来越多地被外包给离岸代工厂。外包制造通过利用规模经济来降低成本，并确保获得最先进的制造技术，但这是以信任为代价的。芯片设计者怎么能相信离岸(不可信)代工厂不会盗版其知识产权(IP)，或通过在芯片中插入硬件特洛伊木马来恶意修改集成电路(IC)？该项目为离岸铸造厂的可靠芯片制造开发了变革性的新解决方案。传统上，芯片的设计考虑了性能和功耗等指标；该项目旨在将安全性作为芯片设计流程的每个步骤中的一个新的同等重要的指标来引入和考虑。拟议研究的结果是一套新的算法，用于设计不仅高性能和低功耗，而且安全的芯片，以防止不可信的离岸代工厂窃取IP或插入硬件特洛伊木马。该项目确保美国的国防机构和商业芯片设计公司能够在不损害信任的情况下访问世界任何地方的顶级铸造厂，从而为美国经济和增强国家安全做出贡献。此外，该项目通过在早期阶段向学生介绍基本的安全概念来培训新一代安全专业人员，并鼓励代表不足的少数群体更多地参与这一关键领域。该研究建立在文献中提出的两种有前途的(和相关的)技术基础上，以实现安全外包IC制造、逻辑加密和拆分制造。这两种方法都是以相同的基本思想为前提的，即只向不可信的铸造商(攻击者)提供设计的部分知识，以限制攻击者S盗版或修改设计的能力。然而，现有的逻辑加密和拆分制造方法在很大程度上是将这些技术作为额外的步骤改进到传统的芯片设计流程中；也就是说，它们将安全性视为事后考虑。该项目旨在从根本上重新思考自动化芯片设计算法(简称EDA算法)，以便在优化芯片性能和功耗的同时提供正式的安全保证和最大限度的安全性。具体地说，这项研究为芯片设计中的三个关键步骤开发了新的安全感知算法：逻辑综合(芯片编译器)；(Ii)逻辑划分(将电路分解为更小的组件)和(Iii)布局(确定每个组件在芯片表面的物理位置)。这些集成到一个新的端到端安全EDA流程中，以实现值得信赖的离岸芯片制造。

Semiconductor chip fabrication is being increasingly outsourced to off-shore foundries. Outsourced fabrication reduces cost by leveraging economies-of-scale and ensures access to the most advanced manufacturing technology, but comes at the expense of trust. How can the chip designer trust that the off-shore (untrusted) foundry does not pirate its intellectual property (IP), or maliciously modify the integrated circuit (IC) by inserting a hardware Trojan in the chip? This project develops transformative new solutions for trustworthy chip fabrication at off-shore foundries. Traditionally, chips have been designed with metrics like performance and power consumption in mind; this project aims to introduce and account for security as a new and equally important metric in each step of the chip design flow. The outcome of the proposed research is a new set of algorithms for designing chips that are not only high performance and low power, but also secure against IP theft or hardware Trojan insertion by an untrusted, off-shore foundry. The project ensures that defense agencies and commercial chip design companies in the United States are able to access top-end foundries anywhere in the world without having to compromise trust, thus contributing to the US economy and enhancing national security. Furthermore, the project trains a new generation of security professionals by introducing students to fundamental security concepts at an early stage, and encourages greater participation of under-represented minorities in this critical area.The research builds upon two promising (and related) techniques that have been proposed in literature to enable secure outsourced IC fabrication, logic encryption and split fabrication. Both approaches are premised on the same basic idea, i.e., to provide the untrusted foundry (the attacker) with only partial knowledge of the design so as to limit the attacker?s ability to pirate or modify the design. However, existing approaches for logic encryption and split fabrication largely retrofit these techniques as extra steps into the conventional chip design flow; that is, they treat security as an afterthought. This project aims to fundamentally re-think automated chip design algorithms (referred to as EDA algorithms) so as to provide formal security guarantees and to provide maximum security while optimizing for chip performance and power. Specifically, the research develops new security-aware algorithms for three critical steps in chip design: logic synthesis (the chip 'compiler'); (ii) logic partitioning (breaking up a circuit into smaller components) and (iii) placement (determining the physical location of each component on the chip surface). These are integrated into a new end-to-end secure EDA flow for trustworthy off-shore chip fabrication.