CAREER: Re-thinking Electronic Design Automation Algorithms for Secure Outsourced Integrated Circuit Fabrication

职业：重新思考安全外包集成电路制造的电子设计自动化算法

• 批准号: 1553419
• 负责人: Siddharth Garg
• 金额: $ 49.74万
• 依托单位: New York University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-06-01 至 2023-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1553419&HistoricalAwards=false
• 关键词: CAREER; Re; thinking; Electronic; Design

Semiconductor chip fabrication is being increasingly outsourced to off-shore foundries. Outsourced fabrication reduces cost by leveraging economies-of-scale and ensures access to the most advanced manufacturing technology, but comes at the expense of trust. How can the chip designer trust that the off-shore (untrusted) foundry does not pirate its intellectual property (IP), or maliciously modify the integrated circuit (IC) by inserting a hardware Trojan in the chip? This project develops transformative new solutions for trustworthy chip fabrication at off-shore foundries. Traditionally, chips have been designed with metrics like performance and power consumption in mind; this project aims to introduce and account for security as a new and equally important metric in each step of the chip design flow. The outcome of the proposed research is a new set of algorithms for designing chips that are not only high performance and low power, but also secure against IP theft or hardware Trojan insertion by an untrusted, off-shore foundry. The project ensures that defense agencies and commercial chip design companies in the United States are able to access top-end foundries anywhere in the world without having to compromise trust, thus contributing to the US economy and enhancing national security. Furthermore, the project trains a new generation of security professionals by introducing students to fundamental security concepts at an early stage, and encourages greater participation of under-represented minorities in this critical area.The research builds upon two promising (and related) techniques that have been proposed in literature to enable secure outsourced IC fabrication, logic encryption and split fabrication. Both approaches are premised on the same basic idea, i.e., to provide the untrusted foundry (the attacker) with only partial knowledge of the design so as to limit the attacker?s ability to pirate or modify the design. However, existing approaches for logic encryption and split fabrication largely retrofit these techniques as extra steps into the conventional chip design flow; that is, they treat security as an afterthought. This project aims to fundamentally re-think automated chip design algorithms (referred to as EDA algorithms) so as to provide formal security guarantees and to provide maximum security while optimizing for chip performance and power. Specifically, the research develops new security-aware algorithms for three critical steps in chip design: logic synthesis (the chip 'compiler'); (ii) logic partitioning (breaking up a circuit into smaller components) and (iii) placement (determining the physical location of each component on the chip surface). These are integrated into a new end-to-end secure EDA flow for trustworthy off-shore chip fabrication.

半导体芯片制造越来越多地外包给离岸代工厂。外包制造通过利用规模经济降低了成本，并确保获得最先进的制造技术，但代价是信任。芯片设计师如何才能相信离岸（不可信）代工厂不会侵犯其知识产权（IP），或者通过在芯片中插入硬件木马来恶意修改集成电路（IC）？ 该项目为离岸代工厂的可靠芯片制造开发了变革性的新解决方案。传统上，芯片的设计考虑到了性能和功耗等指标;该项目旨在将安全性作为芯片设计流程的每个步骤中一个新的同等重要的指标。拟议研究的结果是一套新的算法，用于设计不仅高性能和低功耗，而且还可以防止IP盗窃或不受信任的离岸代工厂插入硬件木马的芯片。该项目确保美国的国防机构和商业芯片设计公司能够在不损害信任的情况下访问世界任何地方的高端代工厂，从而为美国经济做出贡献并增强国家安全。此外，该项目通过在早期阶段向学生介绍基本的安全概念来培养新一代的安全专业人员，并鼓励代表性不足的少数民族更多地参与这一关键领域。该研究建立在文献中提出的两种有前途的（和相关的）技术基础上，以实现安全的外包IC制造，逻辑加密和分裂制造。这两种方法都基于相同的基本思想，即，为不可信的代工厂（攻击者）提供设计的部分知识，以限制攻击者？盗版或修改设计的能力。 然而，现有的逻辑加密和拆分制造方法在很大程度上将这些技术改造为传统芯片设计流程中的额外步骤;也就是说，它们将安全性视为事后的想法。该项目旨在从根本上重新思考自动化芯片设计算法（简称EDA算法），以提供正式的安全保证，并在优化芯片性能和功耗的同时提供最大的安全性。 具体而言，该研究为芯片设计中的三个关键步骤开发了新的安全感知算法：逻辑合成（芯片“编译器”）;（ii）逻辑分区（将电路分解为更小的组件）和（iii）放置（确定每个组件在芯片表面上的物理位置）。这些都集成到一个新的端到端安全EDA流程中，以实现值得信赖的离岸芯片制造。