Electronic Design Automation Algorithms for Signal Integrity Analysis of High Speed Integrated Circuits

用于高速集成电路信号完整性分析的电子设计自动化算法

• 批准号: RGPIN-2014-05429
• 负责人: Dounavis, Anestis
• 金额: $ 2.26万
• 依托单位: University of Western Ontario
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2017
• 资助国家: 加拿大
• 起止时间: 2017-01-01 至 2018-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=637176
• 关键词: Electronic; Design; Automation; Algorithms; Signal

With the rapid advances of technology, system complexity and signal speeds, significant demands are placed on Electronic Design Automation (EDA) tools to provide the same efficiency and accuracy. Innovations in fabrication process technology have significantly reduced the feature sizes of integrated circuits and increased packing densities of chips. Aggressive design objectives such as system on chip coupled with increased operating frequencies require multidisciplinary design methodologies such as electrical, thermal and electromagnetic analysis to accurately model the signal and power integrity of high-speed circuits. As frequency increases, interconnects behave like distributed transmission lines and effects such as ringing, signal delay, distortion, attenuation and crosstalk can severely degrade signal integrity. These effects are observed at the chip, packaging, printed-circuit-board and backplane levels. In general, distributed interconnects are modeled using partial differential equations and when discretized produce large system of equations, which are computationally expensive to solve. Furthermore, due to the increased packing densities of integrated circuits, it is becoming essential to model highly coupled interconnect and power distribution networks with many ports. As a result of these technological advancements, the underlying algorithms of traditional EDA tools have become ineffective and in some cases obsolete in addressing the multidisciplinary nature and computational complexity of modern circuit designs. Currently, the design of multi-port distributed networks is not handled appropriately by circuit simulators and stand as one of the major bottlenecks in design in signal and power integrity analysis. The aim of this research proposal is to develop advanced modeling and simulation algorithms for efficient and accurate analysis and design of high-speed integrated circuits. This will be achieved by extending the scope of macromodeling algorithms to efficiently model large multi-port distributed electromagnetic systems in a unified circuit simulation environment. Furthermore new parallel computing and model order reduction techniques will be developed to reduce the computational complexity of large scale high-speed integrated circuits. The emphasis will be to develop interactive design verification techniques that will enable iterative and repetitive signal and power integrity analysis of large complicated distributed networks. This will lead to better circuit designs, shorter design cycles and lower costs.

随着技术、系统复杂性和信号速度的快速发展，对电子设计自动化（EDA）工具提出了很高的要求，以提供相同的效率和准确性。制造工艺技术的创新已经显著地减小了集成电路的特征尺寸并且增加了芯片的封装密度。诸如片上系统等激进的设计目标加上更高的工作频率，需要多学科的设计方法，如电气，热和电磁分析，以准确地模拟高速电路的信号和电源完整性。随着频率的增加，互连表现得像分布式传输线，并且诸如振铃、信号延迟、失真、衰减和串扰之类的效应会严重降低信号完整性。这些影响在芯片、封装、印刷电路板和背板层面上都可以观察到。一般来说，分布式互连使用偏微分方程建模，并且当离散化时产生大型方程系统，这在计算上是昂贵的。此外，由于集成电路封装密度的增加，对具有许多端口的高度耦合互连和配电网络进行建模变得至关重要。由于这些技术进步，传统EDA工具的底层算法在解决现代电路设计的多学科性质和计算复杂性方面变得无效，并且在某些情况下已经过时。目前，多端口分布式网络的设计没有适当地处理电路仿真器，并在信号和电源完整性分析的设计中的主要瓶颈之一。本研究计划的目的是开发先进的建模和仿真算法，用于高速集成电路的有效和准确的分析和设计。这将通过扩展宏建模算法的范围来实现，以在统一的电路仿真环境中有效地对大型多端口分布式电磁系统进行建模。此外，新的并行计算和模型降阶技术将被开发，以降低大规模高速集成电路的计算复杂度。重点将是开发交互式设计验证技术，使大型复杂的分布式网络的迭代和重复的信号和电源完整性分析。这将导致更好的电路设计、更短的设计周期和更低的成本。