Improving Hardware Security During Design And Deployment

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The proliferation of interconnected devices, such as the Internet of Things, gives embedded computers an outsize role in accessing and affecting parts of our day-to-day lives. The ever-growing complexity of embedded systems presents challenges for maintaining security across their lifecycles. As Canada works towards greater digitalization, the need for knowledge and skills in secure hardware design continues to grow. As hardware forms the foundation of a secure system, we need tools and techniques that support computer hardware engineers to address security concerns. This research program seeks to enhance the security of digital hardware designs and to produce resilient hardware architectures for system-on-chips (SoCs), with the long-term objective to enable holistic and automated security-aware approaches for embedded system design. The program is structured across two overarching research objectives: (1) Understand, identify, and mitigate hardware security weaknesses at the design stage: weaknesses, including unintended bugs or malicious insertions, manifest at different levels of design; some lie within modules while others stem from integrating different components from different vendors. To prevent flaws from presenting as security vulnerabilities in the field, we want to understand what can go wrong during the design process and gain insights into what information is needed to automate the analysis of designs for unintended security issues. (2) Develop and characterize architectures for in-field adaptability to respond to security issues: given the near impossibility of bug-free designs (at least in the context of time-to-market pressures and design trade-offs), we aim to devise different approaches to provide an SoC with the capability to adapt to newly discovered security issues in the field and explore hardware-based solutions for security-related monitoring and intervention. To explore the design space, we will work towards formalizing different notions of "patchability" so that one can perform design space exploration to trade-off costs against potential security benefits when generating a patching infrastructure. The two objectives are interrelated, where insights into complex hardware design weaknesses that escape early detection can inform research in architectures for field adaptability, and where insights from post-deployment patching can inform the analysis of weaknesses in new hardware designs. Research from the proposed program will lead towards new approaches for security-enhanced SoC architectures and insights that will support hardware designers in avoiding security pitfalls. From diving into hardware weaknesses, we will better understand design-time security issues, leading to improved security-enhanced design practices and automated security analysis tools for hardware. Exploring architectures for adaptability leads to new ways to enhance resilience and the lifetime of embedded systems.