在实际器件制造过程中，石墨烯FET的优越性质会因衬底的影响而发生重大变化。本项目提出将石墨烯与衬底相互作用直接融入石墨烯FET器件设计理念，通过实验和第一性原理与量子电热输运理论相结合，系统研究不同衬底对石墨烯FET器件工作性能影响与器件静电放电ESD失效机理。研究以硅基和二维氮化硼与氟化石墨烯为代表的衬底界面，因衬底表面凹凸台阶形貌、堆叠方式、错位等实际工艺原因对石墨烯FET迁移率、跨导、漏电流、增益等器件工作性能的影响，并分析金属电极与石墨烯接触连接在外界强电流与瞬态脉冲电压等干扰下的失效关键因素，通过制造与测试获得在不同衬底上石墨烯FET器件对ESD的响应、维持和崩溃的电压/电流以及失效机理，设计并验证可靠性更高、性能更优的新型石墨烯FET概念器件，为石墨烯信息器件的发展提供理论预测和关键制造技术指导。

Substrate plays a crucial role in preserving the superb operation performance of graphene FETs. In this proposal, we will systematically study the substrate impact and metal-graphene contact reliability on the electronic transport properties of graphene FETs. By combining CVD assembled graphene FET experiments with ab initio theory and NEGF electronic/thermal transport modeling of graphene transistors on various 2D (BN and fluorinated-graphene) and typical 3D silicon-based substrates, we study how the corrugated and terraced substrates change the effective carrier mobility, transconductance, leakage current, and gain of graphene FETs. The break-down mechanism of metal electrode-graphene contacts and ESD properties of graphene FETs will also be investigated. Our work will promote the high performance and reliability of graphene FETs on various substrates.