多核处理器芯片功能延迟测试及低功耗延迟测试

本项目拟重点从事多核系统功能延迟测试及低功耗延迟测试方面的研究。传统的LOC/LOS 延迟测试的初始状态可能是功能无效状态，因而可能导致过测试。本项目拟提出一系列新的技术实现多核处理器芯片功能测试。含：基于结构的非有效状态识别及有效状态识别，功能可测试路径识别，功能转换故障测试码产生及测试精简，功能小延迟缺陷测试码产生及精简，热驱动功能延迟测试。本项目拟提出一种新的低功耗测试压缩方法实现，采用专门针对LOC延迟测试的扫描森林结构及测试响应压缩；采用LFSR及附加变量实现延迟测试种子生成，采用测试点可压缩测试数据容量。含新的扫描结构及测试方法，及测试点管脚开销降低等。提出一种新的ATPG策略可有效地降低捕获功耗。提出新的加权扫描延迟自测试方法及DFT结构。

Functional delay testing has more and more important because conventional LOC/LOS two pattern tests may be unable to identify some potential defects and cause overtesting because the initial state may be invalid. We propose a series of new techniques for functional delay testing:structural analysis based invalid state identification, functional testable path identification, functional transition fault ATPG/test compaction,functional small delay defect ATPG/test compaction for multi-core systems. ..We shall also consider thermal-aware small delay defect testing by maximizing the effect of power droop during testing. New low-power test compression for LOC/LOS delay testing is proposed, which includes a new DFT architecture, ATPG/test compaction scheme, and low-power scan based transition fault BIST based on weighted Pseudo-random test generation. A new low-power deterministic built-in self-test scheme is proposed by using a new low-power test compression scheme and low-power reseeding technique. A new approach is proposed to insert test point and compress test data for LOC delay testing by using a new cost function. A new technique is proposed to reduce pin overhead for extra pins of test points...A new low-power compact test pattern generation method is proposed, which can simultaneously reduce scan-shift power and capture power.