系统芯片的高度集成化对可靠性、功耗、面积等有了更加严格的要求。多核/众核系统芯片测试的研究不但要如何降低测试代价，还必须考虑超大规模系统集成时所面临的挑战。这些挑战含：功耗，温度及面积开销等。片上网络（NOC）是系统芯片的一种实现形式。大型复杂的片上多核/众核系统可能含成百上千个内核，并且每一个内核的规模高达千万门以上，及数十万个触发器。本项目拟提出一系列高效率低成本的测试方法及可测试性设计技术。含：考虑热及能耗的SoC的测试调度，基于ATE通道的带宽调度及结构一致性特性的测试调度，NoC互连测试，内核及路由器测试。 内核测试需充分利用结构一致性的特点降低测试代价。内核测试含基于MISR能容忍unknown信号的测试响应压缩。首先采用自测试策略检测互连的故障,基于已有的故障信息测试路由器。基于连线及路由器故障信息测试内核。内核测试的测试数传输可转化为容错组播问题。

Increasing density of SoCs makes reliability, power consumption and area become more important. We must provide low-cost techniques for multi-/many core system chip testing,and consider power, temperature and many other challenges.Networks-on-chip are one way to implement SoCs. We must be able to handle complex SoCs, which contains hundreds or thousands of cores. Each of these cores contains more than ten million gates, and one hundred thousand flip-flops.We propose a series of effective and low-cost techniques for testng and design for testability.Thermal and energy are considered in the proposed techniques,while identical features of the cores and routers are considered.New test scheduling schemes are proposed based on utilization of ATE channel bandwidths.MISR-based test response compaction is proposed, which tolerates unknown signals. The flow of NoC testing for the new project includes: (1)interconnects are tested locally, (2) test data of routors based on the identical features are proceeded, and (3) a fault-tolerant multicast scheme is followed by using the identified interconnect and router fault information.Other techniques include low-power scan-based BIST for the SoC cores by using an improved weighted scan enable signal based BIST scheme,memory interface testing by using the memory cells to propagate test data,and thermal-driven 3-D stacked SoC testing.