硅基芯-壳结构纳米线CMOS因与传统"Scaling down"工艺相兼容，同时具有极强抑制短沟效应和减少散射增强传导的能力，对于解决10nm以下高集成度CMOS电路系列制约将是很好的一个选择。本项目针对该类器件模拟问题和微纳工艺集成技术困难，以解决10nm尺度芯-壳结构纳米CMOS器件物理模型和精细工艺集成技术为目标，重点从器件结构、传输物理、模型与模拟、精细工艺技术实现等基础性层面开展工作，将芯-壳结构纳米线CMOS功能结构、应力效应、能带工程、工艺集成技术及模型模拟等方面有机结合，提出有助于解决10nm以下CMOS器件设计和电路优化问题的器件物理理论、模拟工具、电路模型和工艺技术实现等层面创新内容和技术解决方案。该项目将阐明芯-壳结构纳米线应用于10nm以下CMOS电路的可能性和功能潜力，有助从基本物理上理解该类结构特性和电路功能，从工艺技术上优化该结构实现其电路性能.

Silicon-based nanowire CMOS with the core-shell structure has not only excellent short-channel effect and enhanced conductance capability due to reduced scattering effect and unqiue low-dimensioal structure,but also is compitable with the traditional CMOS processing,thus, it may be the promise one among the bulk MOSFET alteratives to extend CMOS integratd circuit into 10nm generation beyond... Aiming at the simulation tool issue, compact device/cirucit model problem and the process integration difficulty of such kind of silicon-based nanowire CMOS with the core-shell structure, this project will explore the novel structure, transport mechanism, simulation method and compact modeling, fine process technique from sythesization cnosideration of the function enhancement, strain effect, eneryg band enginnering, channel doping profile, process integration of core-shell nanowire MOSFETs, so to develop the core-shell nanowire MOSFET devie physics theory, provide the new simulation tool, build an efficient compact model, and establish new fine process integration technique. ..The project delivables will help device scientists and circuit designers deeply understand the pontential and function of the silicon-based core-shell nanowire MOSFET application beyond 10nm CMOS integrated circuit, know how to realize the optimized circuit performane from the fine processing technology.