Design and Analysis of Fault-Tolerant Programmable Logic Arrays

为了以更大的芯片密度获得产量的显著提高， 许多半导体制造商已经成功地采用了冗余 存储器芯片设计中的技术，例如64 K DRAM，256 K DRAM， 近年来，由于可编程逻辑阵列的规则结构， （PLA）已经越来越普遍地用于实现布尔逻辑 VLSI中的函数 这项研究正在调查一种替代的PLA 设计冗余，将利用可修复的 部分有缺陷的芯片，以提高芯片产量。 的 研究的目的是设计和修复容错PLA 并将此设计概念应用于任何其它阵列逻辑，例如 可编程阵列逻辑（PAL），以及晶圆级集成（WSI） 设计PLA结构的使用，特别是在 超大规模集成电路微处理器，提高设计生产率，缩短设计 时间，简化了芯片的物理设计，并有利于 实施工程变更。 半导体器件 制造商，不断努力增加芯片的复杂性，减少 速度-功率乘积，增加了可靠性， 具有成本效益的设备。 然而，增加芯片复杂性将 提高了有缺陷芯片的概率， 成本 拟议的研究将提供新的设计和维修 计划，以提高芯片产量。

To attain significant improvements in yield with greater chip density, many semiconductor manufacturers have successfully employed redundancy techniques in the memory chip design, such as 64K DRAMs, 256K DRAMs, etc. Recently, due to the regular structure, Programmable Logic Arrays (PLAs) have become increasingly common for implementing Boolean logic functions in VLSI. This research is investigating an alternative PLA design with redundancy that will exploit the repairability of the partially defective chips in order to enhance the chip yield. The objectives of the research are to design and repair a fault-tolerant PLA and apply this design concept to any other array logic, such as programmable array logic (PAL), as well as Wafer-Scale Integration (WSI) design. The use of PLA structure, particularly in the control portion of a VLSI microprocessor, improves design productivity, shortens design time, simplifies the physical design of the chip, and facilitates the implementation of engineering changes. Semiconductor device manufacturers, continuously strive to increase chip complexity, reduce the speed-power product, increase reliability and produce useful and cost-effective devices. However, increasing the chip complexity would enhance the probability of having defective chips and then increase the cost. The proposed research will provide the new design and repair scheme to enhance the chip yields.