Realistic Modeling of Residual and Thermal Stress in Electronic Devices

研究的主要目的是开发可靠的方法来预测微电子器件结构中的残余（制造）应力和应用热应力水平。此外，该研究还将提出系统地减少制造过程中产生的应力的方法。本研究将适用的结构类型有：半导体晶圆、集成电路芯片、混合电路和异质结激光器。成形过程中产生的应力会对最终产品的可靠性产生不利影响，并通过断裂、掺杂物的异常扩散或有害的电迁移导致器件过早失效。此外，在随后的操作过程中，由于部件内部存在较大的温度梯度，也会产生高应力。由于各种器件材料（如硅和各种薄膜氧化物或金属）之间热膨胀的巨大差异，产生了制造和操作应力。目前预测这种应力的方法是非常近似的。该研究将使用多种固体力学原理来解决有关层状电子结构的一些未解决的问题，特别是晶圆中的界面应力。简单而实用的应力分析公式将用于辅助电子设备的初步机械设计，而有限元应力分析将用于研究必须存在于材料界面的复杂奇异应力系统的详细性质。

The primary objective of the research is to develop reliable methods to predict residual (fabrication) stress and applied thermal stress levels in microelectronic device structures. In addition, the research will also suggest ways to systematically reduce stresses arising during fabrication. The types of structures for which this research will be applicable are: semiconductor wafers, integrated circuit chips, hybrid circuits, and heterojunction lasers. Stresses induced during forming can adversely effect reliability of the end product and cause premature failure of devices via fracture, anomalous diffusion of dopants, or deleterious electromigration. Furthermore, high stresses also occur during subsequent operation due to substantial temperature gradients within components. Both fabrication and operating stresses arise because of the wide disparity of thermal expansion between various device materials, such as silicon and various thin film oxides or metals. Current methods for predicting such stresses are very approximate. The research will use a variety of solid mechanics principles to address some unsolved problems regarding layered electronic structures, particularly interfacial stresses in wafers. Simple but useful stress analysis formulas will be developed to assist preliminary mechanical design of electronic devices, while finite element stress analysis will be employed to study the detailed nature of complex singular stress systems which must exist at material interfaces.