Parallel Algorithms for VLSI Circuit Extraction on Multiprocessors

Banerjee博士的工作重点是VLSI CAD工具，它运行在一类消息传递体系结构上，例如超级立方体。在这项研究中，他将研究工具的算法，这些工具执行从VLSI掩模布局中提取电路的任务。技术方法是将层次描述扁平化为由矩形组成的掩码描述，并在这一级别执行提取。新的多处理器算法将用于加速和准确、快速的电路提取。这些算法将在分布在并行处理器上的数据结构上并行使用区域查询。预计该过程将避免在将VLSI布局区域分割成区域时可能出现的边界效应问题。

The focus of Dr. Banerjee's work is VLSI CAD tools which run on a class of message-passing architectures, such as hypercubes. In this research he will investigate algorithms for tools which perform the task of circuit extraction from VLSI mask layouts. The technical approach is to flatten the hierarchical description into a mask description consisting of rectangles, and perform the extraction at this level. The new multiprocessor algorithms will be used for speedup and accurate, fast-circuit extraction. The algorithms will use region queries in parallel on a data structure distributed over the parallel processor. It is anticipated that this procedure will avoid the boundary effect problems that may arise when splitting a VLSI layout area into regions.