Easily Testable VLSI-Based Systems

本研究针对复杂积体电路之测试与故障分析 (very大规模集成）数字系统。 海耶斯教授将 开发新的设计技术，以提高芯片的可测试性， 系统级和测试生成的高级方法。 的 研究将利用内在的层次结构和规律性， 大多数VLSI设计，虽然认识到这些特性偏离 从理想。 海耶斯研究的主要目标是 了解如何实现极高的故障覆盖率和较短的测试时间 用于大型VLSI电路和系统。 他将调查可测试性 接近常规VLSI芯片的特性。 增加的方法 一般类型的近规则电路的规则性，以提高 将研究其可测试性。 分层测试方法 采用高级电路和故障模型的一代将是 探索，并在测试中使用预先确定的细胞测试的研究 将启动一个非常高级别的电路。 首席研究员是一位杰出的研究人员， 过去十年的成就记录，他很可能会 继续进行一流的研究。 这个提议在技术上是合理的， 构思好，主题好。 这项研究是在 对工业界很重要，对我们理解设计也很重要 超大规模集成电路和系统。

This research addresses testing and fault analysis of complex VLSI (very large scale integrated) digital systems. Professor Hayes will develop new design techniques to enhance testability at the chip and system levels, and high-level methods for test generation. The research will exploit hierarchical structure and regularity inherent in most VLSI design, while recognizing that these characteristics deviate from the ideal. The major objective of Hayes' research is to understand how to achieve very high fault coverage and low test time for large VLSI circuits and systems. He will investigate testability characteristics of nearly regular VLSI chips. Methods of increasing the regularity of general types of nearly regular circuits to enhance their testability will be studied. A hierarchical approach to test generation that employs high-level circuit and fault models will be explored, and a study of the use of predetermined cell tests in testing of very high level circuits will be initiated. The principal investigator is an outstanding researcher with a solid record of accomplishments over the past decade, and he very likely will continue with first-class research. The proposal is technically sound, well conceived and on a good topic. This research is in an area important to industry, and is important to our understanding of design of VLSI circuits and systems.