ROW: Feasibility Study of a New Design Technique for Algorithm Specific VLSI Circuits

本研究的目的是（a）建立一个模型， 预测超大规模集成电路的速度 （B）研究新设计的可行性 用于寻找全局时间优化的VLSI结构的技术 对于一类时间关键的算术计算;（c）以 研究并明确地制定设计权衡， 吞吐量、延迟和芯片面积;（d）开发和自动化 设计最佳超大规模集成电路架构的新程序;及（e） 评估所提出的设计技术的好处。

The objectives of this research are (a) to develop a model for predicting the speed of VLSI (very large scale integrated) algorithms; (b) to study the feasibility of a new design technique for finding global, time-optimized VLSI architectures for a class of time-critical arithmetic computations; (c) to investigate and formulate explicitly design tradeoffs among throughput, latency and chip area; (d) to develop and automate new procedures for designing optimal VLSI architectures; and (e) to evaluate the benefits of the proposed design technique.