Vector Processors for Systolic Arrays

数字信号和图像处理行业持续增长。 然而，许多计算密集型、高端、实时的需求并不 目前正在满足。 这些要求的典型应用领域 通信、雷达/声纳、语音和场景分析、计算机 视觉和图形。 一种新的功能强大的数字处理器 建筑需要满足这一需求。 这项研究是在一个新的 数字处理器设计，有潜力显着增加 在速度、区域速度和成本性能方面。 它可以提供 在一个超大规模集成电路芯片上实现多兆赫的定点和浮点运算。 其创新的位串行处理器间I/O结构使其成为 细粒度脉动阵列应用的候选者。 设计目标 是一个系统，达到十至一百MFLOP每芯片 小型低成本封装中的计算带宽。 这是在 台式超级计算机。 这样的机器可以用作 一般应用中的附加协处理器或嵌入到信号中 和成像系统中。 评论家给了这个分数15，15和18，这是相当高的 相对于所有的分数。 这三位评论家认为， 完善的研究计划，具有良好结果的高概率 进行第二阶段的工作。 他们说，这是一个重要的问题， 可观的回报 解决方案将有助于未来的设计 依赖于快速处理大量数字的仪器。 工作人员的素质很高。

The digital signal and image processing industry continues to grow. However, many compute-bound, high-end, real-time needs are not currently being met. Application areas typifying these requirements are communications, radar/sonar, speech and scene analysis, computer vision and graphics. A new and powerful class of digital processor architectures is required to meet this need. This research is on a new digital processor design that has potential for significant increases in speed, area-speed and cost-performance measures. It can provide multi-megahertz fixed and floating point operation on one VLSI chip. Its innovative bit-serial interprocessor I/O structure makes it a candidate for fine-grain systolic array applications. The design goal is a system which achieves ten to one hundred MFLOP per chip computational bandwidth in a small, low cost package. This is in the class of desktop supercomputers. Such a machine could be used as an attached co-processor in general applications or embedded into signal and imaging systems in application specific environments. Reviewers gave this scores of 15, 15 and 18, which are quite high relative to all the scores. The three reviewers saw this as having al well-developed research plan, with high probability of good results leading to Phase II work. They said it is an important problem with substantial payoff. Solutions will contribute to the design of future instruments that depend on rapid processing of large arrays of numbers. The qualifications of the personnel are excellent.