The Design and Evaluation of a High-Performance Capability Mechanism for a VLSI Processor and its Impact on Software Reliability

中型到大型计算系统的成本中有很大一部分（通常是70%以上）是在软件上。反过来，三分之二左右的软件成本用于维护——修复后来发现的不可避免的程序错误。基于功能的寻址被认为是一种检测和避免许多运行时错误的技术，因为它在实施小保护域、数据抽象和安全模块接口方面很有用。过去提出或实现的一些支持基于能力的寻址的机器一直被其极慢的速度所困扰。本课题的研究目的是设计一种高速能力机制，并在现实技术约束下对其实施情况进行检验和评价。项目从为功能机制制定一组简单但功能强大的原语开始，然后使用这些机制设计和模拟体系结构。然后在模拟器上运行高级基准测试以评估体系结构。

A significant portion (70% and upwards, typically) of the cost of a medium to large-scale computing system is in its software. In turn, two-thirds or so of the software cost goes into maintenance--fixing the inevitable program bugs that are discovered later. Capability-based addressing has been suggested as a technique for detecting and avoiding many run-time errors because of its usefulness in enforcing small protection domains, data abstraction and secure module interfaces. Several machines proposed or implemented in the past to support capability-based addressing have been plagued by their abysmally slow speed. The purpose of the research project is to design a high-speed capability mechanism, examine and evaluate its implementation assuming realistic technological constraints. The project starts with the formulation of a simple, yet powerful set of primitives for the capability mechanism, followed by the design and simulation of an architecture using these mechanisms. High-level benchmarks would then be run on the simulator to evaluate the architecture.