Low-Cost Testing Techniques for VLSI Systems

时序逻辑电路和系统的测试是本文的研究课题。这个问题的解决方案通常需要成本，对于许多应用程序来说，这些成本太高了，无法广泛采用。我们的目标是找到低成本的技术，在保持高故障覆盖率的同时减少时间、面积和测试数据量的开销。这种方法是使用部分扫描和部分内建自测试的概念，它们在时序电路测试中显示出很好的前景。其中一个研究重点是开发新的可测试性度量和扫描元素选择的新标准。第二是系统地避免现有技术中导致高成本的因素。通过使用从关于实际测试生成器的信息导出的扫描元件，正在开发有效的测试算法。使用实际电路的实验工具正在进行大量的经验评估。

Testing sequential logic circuits and systems is the research subject. Solutions to this problem usually require costs that are, for many applications, too formidable to allow wide adoption. The goal is to find low cost techniques that reduce overhead of time, area and test data volume while maintaining high fault coverage. The approach is to use the notions of partial scan and partial BIST, which show promise in testing sequential circuits. One research thrust is to develop new measures of testability and a new criteria for scan element selection. A second is to systematically avoid elements of existing techniques that contribute to high costs. Effective test algorithms are being developed by using scan elements derived from information about the actual test generator. Substantial empirical evaluation with experimental tools using real circuits is being done.