Emulations among Processor Arrays: A Theoretical Study

该研究项目结合了图嵌入和并行算法方面的工作，以研究处理器阵列的各种仿真问题，即由在每种模式下具有处理元件的通信网络组成的并行体系结构。研究集中在与“真实”处理器阵列的设计、编程和实现相关的各种理论问题上。更具体地说，激励研究的研究问题包括尝试：简化并行体系结构的编程，通过允许程序员为理想化体系结构指定算法，然后由实际体系结构模拟该算法；O了解各种互连网络的相对通信能力，方法是根据一般计算，确定基于每个网络的阵列模拟基于其他网络的阵列的效率；O通过让因缺陷而瘫痪的数组模拟自身的无故障版本来实现容错。在拟议的研究过程中获得的理论结果应有助于深入了解所研究问题的“真实”类比。

The research project combines work on graph embeddings and parallel algorithms to study a variety of emulation problems for processor arrays, i.e., parallel architectures that consist of a communication network having processing elements at each mode. The research focuses on a variey of theoretical problems that relate to the design, programming, and implementation of "real" processor arrays. More specifically, the research problems motivating the research include attempts to: o simplify the programming of a parallel architecture, by allowing the programmer to specify an algorithm for an idealized architecture which is then emulated by an actual architecture; o understand the relative communication power of various interconnection networks, by determining how efficiently arrays based on each of the networks can emulate arrays based on the others, on general computations; o achieve fault tolerance, by having an array that has been crippled by defects emulate a fault-free version of itself. The theoretical results obtained in the course of the proposed research should lend insights into the "real" analogs of the problems studied.