Timing Verification and Optimal Clocking of Latch-Controlled Synchronous Digital Circuits

萨卡拉 本文研究锁存控制同步数字系统的时域建模问题. 与边沿触发触发器相反，电平敏感锁存器的使用近年来已经变得相当普遍，因为锁存器很容易在MOS VLSI中实现，MOS VLSI是构建数字系统的领先技术。 一个一致的理论框架，描述的时间限制，必须满足这样的系统正常运行正在开发。 这个框架被用来开发有效的算法，定时验证和最佳时钟。 这两个问题都需要求解大型线性规划（LP）。 这些LP的特殊结构将被用来减少求解时间，使算法可以用于交互式设计环境。 这个框架和相关算法的实际意义正在实际的工业VLSI设计实验评估。

Sakallah This research is on the temporal modeling of latch- controlled synchronous digital systems. The use of level- sensitive latches, as opposed to edge-triggered flip-flops, has become quite common in recent years because latches are easily implemented in MOS VLSI, the leading technology for building digital systems. A consistent theoretical framework for describing the timing constraints which must be satisfied by such systems for proper operation is being developed. This framework is being used to develop efficient algorithms for timing verification and optimal clocking. Both of these problems require the solution of large linear programs (LPs). The special structures of these LPs will be utilized to reduce the solution time so that the algorithms can be used in an interactive design environment. The practical significance of this framework and associated algorithms is being assessed experimentally on actual industrial VLSI designs.