Timing Issues in the Design of Digital Systems

这项研究是在时序验证和优化框架设计一个完整的数字系统（如微处理器）。该研究建立在一个广泛使用的同步时序分析模型和一个有效的方法来估计门和线延迟。 该模式正在扩大，以包括相关的功能信息，以提高准确性。 该框架的组成部分是：设计分解，隔离关键元素;路径延迟计算器;算法寻找同步器组件;时钟分析算法;一个符号顺序时序验证组件;一个混合时序逻辑模拟器;和设计优化器。

This research is on a timing verification and optimization framework for designing an entire digital system (e.g. a microprocessor). The research builds on a widely used model for synchronous timing analysis and an efficient method for estimating gate and wire delays. The model is being extended to include relevant functional information in order to enhance accuracy. Components of the framework are: design decomposition to isolate critical elements; a path delay calculator; algorithms for finding synchronizer components; clock analysis algorithms; a symbolic sequential timing verification component; a hybrid timing-logic simulator; and design optimizers.