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Low Temperature Depositions and Growth of Dielectric Films Using Electron Cyclotron Resonance Source

Low Temperature Depositions and Growth of Dielectric Films Using Electron Cyclotron Resonance Source
使用电子回旋共振源的介电薄膜的低温沉积和生长
批准号:
9111968
负责人:
Stella Pang
金额:
$7.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
1991
资助国家:
美国
项目状态:
已结题
起止时间:
1991-08-15 至 1994-07-31

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中文摘要
翻译
对于亚微米尺寸的器件和密集封装的集成电路,低工艺温度是必不可少的。虽然大多数制造步骤都可以在低温下进行,但唯一的例外是介电层的形成。为了获得不同用途的低温介质材料,我们建议使用电子回旋共振(ECR)源进行沉积和生长。ECR源提供的高效率的气体解离和激发使活化能降低,并产生高密度的反应自由基。拟议的工作还有两个新的推动力。通过调节两个进气口的进气量来研究选择性激发和解离的效果:一个进气口位于ECR腔内,另一个进气口靠近样品台。第二个重点是通过控制活性物质的到达速度来控制表面反应。通过提供对这些参数的控制,可以获得高质量的薄膜、新的介质材料和高纵横比特征的有效阶跃覆盖。该项目有三个目标:(1)低温栅电介质的沉积和生长,重点是为单晶片加工提供高质量的电学和合理的沉积速率;(2)用于多层互连的沉积平坦化介质,主要问题是整体平坦化程度高和良好的电学性能;(3)均匀厚度的高深宽比特征的共形阶跃覆盖的反应时间控制。
英文摘要
For devices with submicrometer dimensions and densely packed integrated circuits, low processing temperature is essential. While most of the fabrication steps can be carried out at low temperature, the only exception is the formation of dielectric layer. To obtain low temperature dielectric materials for different applications, we propose using electron cyclotron resonance (ECR) source for deposition and growth. The high efficiency for gas dissociation and excitation provided by ECR source allows the activation energy to be lowered and high density of reactive radicals to be generated. There are two additional new thrust for the proposed work. The effect of selective excitation and dissociation will be studied by adjusting the gas injection to the two gas inlets: one by the ECR cavity and one around the sample stage. The second focus is on controlling the surface reaction by timing the arrival rate of the reactive species. By providing control of these parameters, high quality films, new dielectric materials, and effective step coverage for high aspect ratio features can be obtained. There are three objectives of this proposed project: (1) deposition and growth of low temperature gate dielectric, the focus is on high electrical quality and reasonable deposition rate for single wafer processing; (2) deposit planarized dielectric for multilevel interconnections, a major issue is on high degree of global planarization and good electrical properties; (3) reaction time control for conformal step coverage of high aspect ratio features with uniform thickness.
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