Implementation of High Bandwidth Memory Systems

Wulf这个项目正在建造和测量实验存储系统，使处理器的高数据速率与存储部件的低随机访问数据速率相匹配。目标是在编译时检测内存引用流，并使用智能内存控制器在运行时预取这些流。存储器控制器可以使用诸如页面模式、半字节模式或Rambus之类的存储器系统的特征来最大化存储器部分的数据速率。然后，它对流进行缓冲，直到处理器请求数据。该项目包括编译器研究以及内存控制器体系结构的研究。这类似于克雷超级计算机等机器上的矢量化工作，但更一般，因为智能内存控制器可以为处理器速度、内存功能和程序特征的任意组合而设计。

Wulf This project is building and measuring experimental memory systems that match the high data rates of processors with the low random access data rates of memory parts. The goal is to detect streams of memory references at compile time and use a smart memory controller to prefetch the streams at run time. The memory controller can use features of the memory system such as page mode, nibble mode, or Rambus to maximize the data rates of the memory parts. It then buffers the streams until the processor asks for the data. The project includes compiler research as well as research into the architecture of the memory controllers. This is similar to the vectorization efforts on such machines as the Cray supercomputers, but more general since a smart memory controller can be designed for any combination of processor speeds, memory features, and program characteristics.