Analog Computation and VLSI Architectures for Contraction Mappings

这个项目将尝试开发一类新的循环网络。网络架构的灵感来自于最近基于迭代变换理论的图像编码及其相关的逆问题。pi的目的是将我们的研究限制在可以在亚阈值模拟VLSI中物理实现的网络上。采用这种方法，实现高质量算术运算的模拟组件是不必要的。事实上，对于理想线性行为的显著偏离是可以容忍的，只要这些偏离是跨芯片可重复的。作为一个具体的应用程序，他们将考虑数据压缩和解压缩的任务。压缩是通过将电子电路松弛到稳定状态来完成的，而压缩可以离线进行，也可以使用自适应模拟VLSI神经网络架构进行。对于硬件压缩，他们建议使用一种学习权重和连接拓扑的学习算法。因此，门控和开关电流的能力是这些网络运行的核心。本研究的主要目的是设计和表征在一维上实现所需转换的电路。这项研究的成功结果有可能使压缩和解压缩技术适用于所有低功耗应用。＊＊＊

9313934 Andreou This project will attempt to develop a new class of recurrent networks. The architecture of the networks is inspired by recent work on image encoding based on iterated transformation theory and it's associated inverse problems. The PIs purpose to restrict our investigation to networks that can be physically implemented in subthreshold analog VLSI. With their approach analog components that implement high quality arithmetic operations are unnecessary. Indeed, significant departures from ideal linear behavior can be tolerated, provided that these departures are reproducible across chips. As a concrete application they will consider that task of data compression and decompression. Compression is accomplished by the relaxation of an electronic circuit to a steady state while compression is preformed either off-line or with an adaptive analog VLSI neural network architecture. For hardware compression they propose to use a learning algorithm that learns both the weight and the connection topology. Hence, the ability to gate and switch electrical current is central to the operation of these networks. The main thrust of this investigation is to design and characterize the circuits that implement the required transformations in one dimension. A successful outcome to this investigation has the potential for making compression and decompression technology available for all low-power applications. ***