Parallel Algorithms for Synthesis and Test

这项研究是关于开发在并行计算机上运行的电路设计和测试算法。 这些包括有效的，异步的，便携式的并行算法：（A）组合电路的综合;和（B）组合和时序电路的测试生成和故障模拟。 算法是使用一个环境，使其能够在广泛的MIMD机器的端口CAD应用程序编写的。 此外，它们被设计为允许计算和通信的最大重叠。 这些算法正在许多并行平台上进行测试。

This research is on developing circuit design and test algorithms that run on parallel computers. These include efficient, asynchronous, portable parallel algorithms for: (A) synthesis of combinational circuits; and (B) for test generation and fault simulation of combinational and sequential circuits. Algorithms are being written using an environment that makes it possible to port CAD applications across a wide range of MIMD machines. In addition they are designed to allow a maximum overlap of computation and communication. The algorithms are being tested on numerous parallel platforms.