Efficient Testing Paradigms and Diagnosable Design Methodologies for Analog Integrated Circuits and Systems

这项研究是关于高频、线性和非线性混合信号电路和系统的测试范例。BIST(内置自检)和可测试性设计中的问题正在得到解决。硬故障(断路或短路)和软故障(与额定元件值的偏差)的故障模型正在开发中。在BIST设计中，采用了高速、低功耗、电流模式复制器作为采样/保持电路，在3.3V电源电压下实现了10 ns/采样、0.1%的精度。同时使用了cmos和Bicmos技术。可测试性设计工作的重点是正确选择组件值和拓扑结构，以提高可测试性和可诊断性。将元件取值问题描述为一个以可测试性策略为参数的优化问题。新方法正在实际电路上进行测试。

This research is on test paradigms for high-frequency, linear and nonlinear mixed signal circuits and systems. Issues in BIST (Built-In Self-Test) and design for testability are being addressed. Fault models for hard faults (open or short circuits) and for soft faults (deviations from nominal component values) are being developed. For BIST design, a high speed, low power, current mode copier is employed as the sample/hold circuit to achieve 10 ns/sample at 0.1% accuracy under 3.3V power supply. Both CMOS and BiCMOS technology are being used. Design for testability work focuses on properly selecting component values and topological structure to increase testability and diagnosability. The problem of determining component values is formulated as an optimization problem which includes testability strategy as a parameter. The new methods are being tested on realistic circuits.