RESEARCH INITIATION AWARD: Kinetics and Structure of Vertical Isolation for VLSI Circuits Formed by Low Temperature Oxidation of Silicon

本研究将研究硅与硅化铜接触时硅的低温氧化。这些现象的动力学、氧化层的表征，以及利用依赖于生长速率的取向在集成电路中形成垂直隔离氧化物的方法，都将被研究。在室温下，当暴露于空气中时，硅化铜在硅和硅化物界面之间形成氧化层。氧化层在几周内生长到几微米的厚度。生长动力学，将被表征以获得活化能，底物取向，移动物种的身份（使用植入的制造商），以及掺杂剂和杂质的影响。生长氧化物的完整性将通过电测量（MOS电容器结构，I-V, C-V），离子束分析（成分，密度和杂质）和透射电子显微镜（微观结构）来量化。＊＊＊

9410399 Alford This investigation will study the low temperature oxidation of Si in contact with Cu-Silicide. The kinetics of the phenomena, characterization of the oxide layer, and use of the orientation dependence on growth rate to form vertical isolation oxides in integrated circuits shall be investigated. At room temperature Cu-silicide forms an oxide layer between the Si and silicide interface when exposed to air. The oxide layer grows to a thickness of several microns in a period of weeks. The growth kinetics, will be characterized to obtain activation energy, substrate orientation, identity of moving species (use of implanted makers), and influence of dopants and impurities. The integrity of the growth oxide will be quantified by electrical measurements (MOS capacitor structures, I-V, C-V), ion-beam analysis (composition, density, and impurities), and transmission electron microscopy (microstructure). ***