Innovative Technology for III-V/Si Optoelectronic IntegratedCircuits

[9410905]在即将到来的信息时代，当通信和计算系统融合时，将光子学和电子学结合起来的方案变得越来越重要。一个理想的方案是将光子学和电子学集成在一起，形成光电集成电路（OEIC）。这种OEIC不仅可以提供高效的O/E和E/O接口，而且在大规模并行互连和信号处理中也有应用。由于晶体管和光学器件（激光器和探测器），电子和光子学的主力，主要分别由硅和III-V化合物半导体制成，最明智的OEIC应该将III-V光电子与Si电子结合起来。如果这种III-V/Si OEIC技术成为可能，就可以探索光电子学与纳米电子学和微加工集成等令人兴奋的新领域。这些新地区未来的影响可能非常重大。硅基OEIC的一个基本问题是不能在硅衬底上可靠地形成高质量的III-V化合物外延。此外，由于III-V材料与Si材料的工艺不相容，形成III-V/Si OEIC的集成工艺尚未开发。为了解决这些技术瓶颈，本研究将重点关注三个主题：(1)开发在硅衬底上集成III-V外延层的可行技术，(2)开发将III-V光学元件与硅电子电路集成的工艺，以及(3)展示功能性III-V/Si OEIC。＊＊＊

9410905 Lo When communication and computing systems merge in the coming information age, schemes of interfacing photonics and electronics become increasingly important. One ideal scenario will be integrating photonics and electronics together to form optoelectronic integrated circuits (OEIC's). Such OEIC's will not only provide efficient O/E and E/O interfaces but also have applications in massively parallel interconnect and signal processing. Since transistors and optical devices (laser and detectors), the workhorses for electronics and photonics, are mostly made of silicon and III-V compound semi-conductors respectively, the most sensible OEIC's should combine III-V optoelectronics with Si electronics. If the technology for such III-V/Si OEIC's becomes available, exciting new areas such as the integration of optoelectronics with nanoelectronics and micromachining can be explored. The future impact of these new areas might be very significant. One fundamental problem for Si-based OEIC's is that high quality III-V compound epitaxy can not be formed reliably on Si substrates. Besides, the integration process of forming III-V/Si OEIC's has not been developed, hindered by the process incompatibilities between III-V and Si materials. To solve these technical bottlenecks, this research will focus on three subjects: (1) to develop viable technology to integrate III-V epitaxial layers on silicon substrates, (2) to develop processes to integrate III-V optical components with silicon electronic circuits, and (3) to demonstrate functional III-V/Si OEIC's. ***