Analytical Model of Superscalar Processor Performance

跟踪驱动模拟器(TD)被处理器架构师广泛用于准确评估处理器设计的预期性能。虽然TDS是必要和有用的，但它也有一些缺点。真实程序的轨迹通常非常大且存储成本很高，而且轨迹的模拟可能非常耗时。此外，模拟不会给出决定性能的因素的特征，因此不能建议进行特定的更改以提高性能。这项研究的两个目标是(1)研究TDS的替代方案，以准确量化处理器性能；(2)寻求确定决定超标量处理器性能的因素。这项工作将涉及开发一种机器行为的分析模型，在此基础上可以计算处理器的性能，而不需要乏味的轨迹驱动模拟。希望同样的分析模型除了提供有用的工具外，还将提供超标量处理器性能的表征。这种特征可以潜在地揭示控制处理器性能的基本规律，这些规律可以通过数学公式来表示。在本研究项目中，处理器性能被建模为程序并行性和机器并行性的组合。程序并行性由两个分布函数表示，这两个分布函数由基准程序的执行轨迹派生，并捕获程序中的控制和数据依赖关系。该推导类似于对从时间域到变换域的执行轨迹执行一种类型的变换。因此，这两个分布函数可以看作是程序并行性的简明频谱表示。机器并行度表示处理器中可用于并行处理指令的资源。机器被建模为基本组件的网络或电路，例如缓冲器和标量流水线。将开发组件的宏观模型以及它们的串联和并行互连模型。利用这种模型微体系结构电路，可以对复杂的超标量处理器进行有效和严格的建模。虽然这项研究在本质上看起来有点理论性，但需要进行大量的实验，这是意料之中的。该计划是与具有极长踪迹的现实程序以及实际指令集体系结构的广泛最先进实现一起工作。使用阿尔法21164和Power PC620设计以及SPEC92沈基准套件作为主要的实验车辆。

Trace-driven simulators (TDS) are widely used by processor architects to accurately assess the expected performance of a processor design. While necessary and useful, TDS have some shortcomings. Traces of realistic programs are usually very large and expensive to store, and simulation of traces can very time consuming. Furthermore, simulation does not yield a characterization of the factors that determine performance, and hence can not recommend specific changes to enhance performance. The two-fold objectives of this research are (1) to investigate alternatives to TDS for accurately quantifying processor performance; and (2) to seek to characterize factors that determine superscalar processor performance. The effort will involve developing an analytical model of machine behavior, based on which processor performance can be computed without requiring tedious trace-driven simulation. It is hoped that the same analytical model, in addition to providing a useful tool, will also provide a characterization of superscalar processor performance. This characterization can potentially reveal fundamental laws governing processor performance that can be mathematically formulated. In this research project, processor performance is modeled as a composition of program parallelism and machine parallelism. Program parallelism is represented by two distribution functions that are derived from the execution trace of benchmark and captures the control and data dependencies in the program. This derivation is analogous to performing a type of transform on the execution trace from the time domain to the transformed domain. Consequently the two distribution functions can be viewed as concise spectral representation of the program parallelism. Machine parallelism represents the resources available in the processor for the concurrent processing of instructions. A machine is modelled as a network, or circuit, of primitive components, e.g. buffers and scalar pipelines. Macro models of the components and the model for their serial and parallel interconnections will be developed. With such a circuit of model microarchitectures, complex superscalar processors can be effectively and rigorously modeled. While the research appears somewhat theoretical in nature, a great deal of experimentation is required and expected. The plan is to work with realistic programs with extremely long traces as well as a wide range of state-of-the-art implementations of real instruction set architectures. The Alpha 21164 and the Power PC 620 designs and the SPEC92 Shen benchmark suites are used as the primary experimentation vehicles.