CISE Educational Infrastructure: "Modern Processor Design: A New Computer Engineering Course"

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This award is for the development of a course on modern processor design that will focus on instruction level parallel (ILP) processing in single chip processors and will include techniques for superpipelined and superscalar processor design, instruction scheduling techniques for ILP type processor, and instruction-level performance evaluation and characterization. A new processor design methodology involving experimentation and quantitative analysis of the performance impact of specific design features will be presented in the course. Dr. Shen will be writing a textbook as well as a set of lecture notes for distribution to other institutions. This award is for the development of a senior-level computer engineering course on modern processor design. The course will address contemporary processor design techniques relevant to the design of current and future generation processors that exploit instruction level parallelisms. Examples include superpipelined, superscalar, supersymmetry and Very Long Instruction Word (VLIW) processors. A textbook and a set of lecture notes will be disseminated as part of this project.