NSF Young Investigator: New Directions in High-Performance VLSI Layout

性能驱动布局的现实公式是本研究的重点。人们正在寻求精确的电路延迟模型。这些模型包括技术参数，如电容、电阻、电感等。该方法是研究延迟最优树来定义可实现路由性能的包络。研究了近似最优布局的构造方法。此外，路由问题被重新定义为一个构建允许循环的低延迟路由图的问题。这样设计的优点是可以容忍由于制造缺陷或电迁移引起的某些类型的开放故障。

Realistic formulations of performance-driven layout are the focus of this research. Accurate models of circuit delay are being sought. These models include technology parameters, such as capacitance, resistance, inductance, etc. The approach is to study delay-optimal trees to define an envelope of achievable routing performance. Methods for constructing near-optimal layouts are being investigated. Additionally, the routing problem is being recast as one of constructing low-delay routing graphs where cycles are allowed. This can have the advantage of designs being tolerant to certain types of open faults due to manufacturing defects or electro-migration.