Reachability Computation Using the Extended Finite State Machine Model and its Application to Automatic Test Generation

这项研究致力于计算用高级语言描述的VLSI设计的可达状态，并将这些结果应用于自动测试模式生成(ATPG)。正在探索以符号方式计算从初始状态可达的状态集的方法。正在使用扩展的有限状态机(ESFM)模型，该模型可以表示通信协议和硬件行为。一个关键的想法是，该模型允许使用任意状态变量，如布尔和算术，这将提供计算效率。正在开发将VHDL语言中的设计自动转换为ESFM的方法和原型工具。这些方法和技术正在应用于ATPG的时序电路测试。

This research addresses computation of reachable states for VLSI designs described in high-level languages and the application of these results to automatic test pattern generation (ATPG). Methods to compute symbolically the set of states reachable from an initial state are being explored. An extended finite state machine (ESFM) model, which can represent communication protocols and hardware behavior, is being used. A key idea is that the model allows use of arbitrary state variables, such as boolean and arithmetic, which will provide efficiency in computation. Methods and prototype tools to convert automatically a design in VHDL to an ESFM are being developed. These methods and techniques are being applied to ATPG for sequential circuit test.