PDS: Pursuing a Petaflop: Point Designs for 100TF Computers Using PIM Technologies

高性能计算的当前技术水平存在两个主要问题。首先，最高端机器的成本远远超过了广泛部署的可能性，其次(更关键的是)这些机器的软件环境充其量是笨拙的，只能勉强维持硬件所能提供的性能的一小部分。这个问题的论点是，很大一部分问题源于我们历史上分离内存和CPU逻辑部分。单个CPU时钟频率和内部体系结构继续加速，因此需要来自内存子系统的不断增加的带宽。这些速率已经远远超过了我们最密集的DRAM内存部件(控制系统成本所需的)的带宽能力，而且随着时间的推移，差距将会扩大。最终结果是复杂的内存层次结构，这反过来又增加了有效处理这些层次结构的成本和软件复杂性。一种新技术正在出现，以弥补这一根本缺陷：在一块芯片上结合高密度DRAM和非常大量的逻辑。这种能力允许称为内存中处理(PIM)的新体系结构将计算放在内存宏的旁边，甚至在内存宏的内部，那里有大量的原始带宽。第一个这样的芯片EXECUBE集成到4Mbit DRAM芯片上，8个完整的CPU配置在3D二进制超立方体中，并能够用作MIMD和SIMD组织的MPP的单芯片类型的构建块。该项目的目标是着眼于在未来十年利用PIM技术的潜力，并证明它们有望实现高效的解决方案。要使用的方法包括配置和研究一些针对几类有趣的问题具有100万亿(Fl)操作潜力的“点设计”MPP，然后利用这些体系结构的新颖功能，以及匹配的系统软件和软件开发工具，以不仅允许卓越的性能，而且可以极大地简化编程环境的方式来攻击它们。

There are two major problems with the current state of the art in high-performance computing. First, the cost of the very highest end machines lies far beyond the point where widespread deployment is feasible, and second (and more critical) the software environments for these machines are awkward at best, and capable of eking out only fractions of the performance that the hardware is capable of supplying. The thesis of this is that much of the problem stems from our historical separation of memory and CPU logic parts. Individual CPU clock rates and internal architectures continue to accelerate, and thus require ever increasing amounts of bandwidth from the memory subsystem. These rates have far exceeded the bandwidth capabilities of our densest DRAM memory parts (needed to control system costs), and the gap will widen over time. The net effect is complex memory hierarchies, which in turn drives cost and software complexity in addressing these hierarchies efficiently. A new technology is emerging to counter this fundamental defect: the combination on one chip of both dense DRAM and very significant amounts of logic. This capability permits new architectures termed Processing-In-Memory (PIM) to place computing either right next to, or even inside of, the memory macros, where there are huge amounts of raw bandwidth. The first such chip, EXECUBE, integrated onto a 4Mbit DRAM chip 8 complete CPUs configured in a 3D binary hypercube, and was capable of being used as a one chip-type building block for MPPs of both MIMD and SIMD organization. The objective of this project is to look at utilizing PIM technology potentials over the next decade and demonstrate that they promise efficient solution. The approach to be used involves configuring and studying some "point design" MPPs with 100 tera(fl)op potential for several interesting classes of problems, and then utilizing the novel features of these architectures, along with matching system software and software development tools, to attack them in ways that may permit not only exceptional performance, but also greatly simplified programming environments.