SBIR Phase II: In-Line Process Monitoring & Control for Poly-Silicon Formation Inside Cluster Tools

*9631216所罗门这个小型企业创新研究第二阶段项目将开发傅立叶变换红外(FT-IR)仪器，用于在线监测和控制多晶硅和介电制造过程中的群集式工具。建立了一种基于傅里叶变换红外光谱的多晶硅薄膜和介质薄膜厚度、掺杂多晶硅薄膜的自由载流子浓度和散射率的测定方法。该技术适用于多层和图案化的样品，当晶片处于丛集工具的冷却室中时，可以实时进行测量和分析。德州仪器在第一阶段对集束仪器进行的现场测试确定了测量掺杂和非掺杂多晶膜、相对较厚(250 Nm)的场氧化物、薄(10 Nm)栅氧化物和图案化晶片的能力。双方将共同努力：1)开发一种在集群工具上测试改进的在线FT-IR工艺监测器；2)开发强大的自动化软件，用于分析毛毯和图案化晶片上的多层多晶硅/介质薄膜；3)开发用于测量介电和多晶硅性能一致性的高速晶片测绘系统；以及4)开发工艺监测、优化和控制软件及分析方法。该项目将产生坚固耐用的多用途仪器，用于在线监测和控制在组合工具中执行的各种制造过程。该项目可以提高集成电路(IC)的生产成品率，消除因未检测到的不合规格的晶圆而导致的报废批次，减少人力需求，并缩短从启动到高产生产的时间。晶片测绘工具还将用于许多其他IC制造工艺的质量控制，如外延注入和离子注入。***

*** 9631216 Solomon This Small Business Innovation Research Phase II Project will develop Fourier transform infrared (FT-IR) instrumentation for in-line monitoring and control of poly-silicon and dielectric fabrications processes within a cluster tool.. An FT-IR based method to determine polysilicon and dielectric film thicknesses, and free carrier concentrations and scattering rates of doped poly films has been developed. The technique is adaptable to multilayered and patterned samples, and the measurement and analysis can be performed in real-time, while the wafer is in the cooldown chamber of the cluster tool. Field tests in Phase I on a cluster tool at Texas Instruments established the capability to measure doped and undoped poly films, relatively thich ((250 nm) field oxides, thin ((10nm) gate oxides, and patterned wafers. A collaborative effort will be made to: 1) develop test a refined in-line FT-IR process monitor on the cluster tool, 2) Develop robust automated software for analysis of multilayered poly/dielectric films on blanket and patterned wafers, 3) Develop a high speed wafer mapping system for measuring uniformity of dielectric and poly properties, and 4) Develop process monitoring, optimization and control software and analysis methodology. This project will result in rugged multi-applications instrumentation for in-line monitoring and control of a wide range of fabrication processes performed in a cluster tool. This project can increase integrated circuits (IC) production yield, eliminate scrapped batches due to undetected out-of-spec wafers, reduce manpower requirements, and reduce the time between start-up and high yield production. The wafer mapping tool will also be useful for quality control of many other IC fabrication processes such as epi and ion implantation. ***