Unified Algorithms and Architectures for Low-Power Wireless Video

对实时图像和视频通信的需求对功率和数据速率受限的通信链路提出了前所未有的要求。目前的通信系统主要是为以固定速率进行数据通信而设计的，并且与视频数据的匹配性较差，视频数据的容错性更强，并且具有速率波动的特征。无线信道的质量也可能变化很大，视频编码和传输应该适应这些变化的条件。现有的硬件实现同样不灵活，是针对预先指定的条件和固定的功耗独立设计的。因此，当前的视频压缩器、无线调制解调器和它们的硬件之间的匹配性往往很差。本研究致力于视频通信组件的联合设计，以最大化视频通信组件的整体系统设计，最大化系统的整体性能。在无线通道低功耗图像和视频传输方面取得前所未有的性能的同时，这项研究还开发了一种强大而通用的新方法，用于直接将芯片设计与信号处理算法和整体系统优化相结合。通过信源编码、信道编码和VLSI计算的自适应联合优化，该研究在无线通信链路上的端到端视频传输方面取得了显著的改善。不是为信源编码器、信道编码器和VLSI硬件选择固定的操作点，而是正在开发支持各种操作点的动态可调编码器和硬件。实现这一总体系统目标的具体研究任务包括：(1)基于多分辨率数据结构和对误码的容错率失真优化编码器的开发；(2)支持多通道可变速率和质量数据传输的多分辨率信道编码方法；(3)通过动态算法变换(DAT)实现硬件的实时重构，以实现在不同操作点的低功耗操作；以及(4)在系统总体功率约束下对上述三个组件进行联合优化。

The demand for real-time image and video communications places unprecedented demands on power and data-rate-limited communication links. Present day communication systems are primarily designed for data communications at a fixed rate and are poorly matched to video data, which is more tolerant of errors and is characterized by fluctuating rates. The quality of wireless channels can also vary greatly, and the video coding and transmission should be adapted to these changing conditions. Existing hardware implementations are equally inflexible, being designed independently for pre-specified conditions and a fixed power consumption. The match between current video compressors, wireless modems, and their hardware is thus often very poor. This research addresses the joint design of video communication components to maximize the overall system design of video communication components to maximize the overall system performance. While achieving unprecedented performance in low-power image and video transmission over wireless channels, this research also develops a powerful and general new methodology for directly coupling chip design with signal processing algorithms and overall system optimization. The research obtains dramatic improvements in end-to-end video transport over wireless communication links through adaptive, joint optimization of source coding, channel coding, and VLSI computation. Instead of selecting fixed operating points for the source coder, channel coder, and the VLSI hardware, dynamically adjustable coders and hardware supporting a variety of operating points is being developed. Specific research tasks to achieve this overall system goal include: (1) the development of rate-distortion-optimized coders based on multi-resolution data structures and tolerance to bit errors; (2) multi- resolution channel coding methods supporting variable rate-vs.-quality data transmission for multiple channels; (3) real-time reconfigurable hardware via Dynamic Algorit hm Transformations (DAT) to achieve low-power operation at various operating points, and, (4) joint optimization of the above three components subject to overall system power constraints.